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1 of 60 rev: 011206 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds21448 is a quad-port e1 or t1 line interface unit (liu) for short-haul and long-haul applications. it incorporates four independent transmitters and four independent receivers in a single 144-pin pbga or 128-pin lqfp package. the transmit drivers generate the necessary g.703 e1 waveshapes in 75 ? or 120 ? applications and the dsx-1 or csu line build-outs of 0db, -7.5db, -15db, and -22.5db for t1 applications. applications integrated multiservice access platforms t1/e1 cross-connects, multiplexers, and channel banks central-office switches and pbx interfaces t1/e1 lan/wan routers wireless base stations ordering information part* temp range pin-package ds21448 0c to +70c 144 te-pbga ds21448+ 0c to +70c 144 te-pbga ds21448n -40c to +85c 144 te-pbga ds21448n+ -40c to +85c 144 te-pbga ds21448l 0c to +70c 128 lqfp ds21448l+ 0c to +70c 128 lqfp ds21448ln -40c to +85c 128 lqfp ds21448ln+ -40c to +85c 128 lqfp + denotes lead-free/rohs-compliant package. * all devices rated at 3.3v. pin configurations appear in section 11 . features four complete e1, t1, or j1 lius supports long- and short-haul trunks internal software-selectable receive-side termination for 75 ? /100 ? /120 ? 3.3v power supply 32-bit or 128-bit crystal-less jitter attenuator requires only a 2.048mhz master clock for e1 and t1, with the option to use 1.544mhz for t1 generates the appropriate line build-outs with and without return loss for e1, and dsx-1 and csu line build-outs for t1 ami, hdb3, and b8zs encoding/decoding 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz clock output synthesiz ed to recovered clock programmable monitor mode for receiver loopbacks and prbs pattern generation/ detection with output for received errors generates/detects in-band loop codes, 1 to 16 bits, including csu loop codes 8-bit parallel or serial interface with optional hardware mode muxed and nonmuxed parallel bus supports intel or motorola detects/generates blue (ais) alarms nrz/bipolar interface for tx/rx data i/o transmit open-circuit detection receive carrier loss (rcl) indication (g.775) high-z state for ttip and tring 50ma rms transmit current limiter jtag boundary scan test port per ieee 1149.1 meets latest e1 and t1 specifications including ansi.403-1999, ansi t1.408, at&t tr 62411, itu g.703, g.704, g.706, g.736, g.775, g.823, i.431, o.151, o.161, etsi ets 300 166, jtg.703, jti.431, tbr12, tbr13, and ctr4 ds21448 3.3v e1/t1/j1 quad line interface www.maxim-ic.com downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 2 of 60 table of contents 1. block diagrams ................................................................................................................. ....... 5 2. pin description .......................................................................................................................... 7 3. detailed description ........................................................................................................... .13 3.1 ds21448 and ds21q348 d ifferences ...................................................................................... 13 4. port operation ................................................................................................................. ...... 14 4.1 h ardware m ode ......................................................................................................................... 14 4.2 s erial p ort o peration .............................................................................................................. 15 4.3 p arallel p ort o peration ......................................................................................................... 18 4.3.1 device power-up and reset...................................................................................................... .......... 18 4.3.2 register map................................................................................................................... ..................... 18 4.3.3 control re gisters .............................................................................................................. ................... 19 5. status registers............................................................................................................... ..... 23 6. diagnostics ................................................................................................................... ........... 28 6.1 i n -b and l oop -c ode g eneration and d etection ...................................................................... 28 6.2 l oopbacks ............................................................................................................................... ... 31 6.2.1 remote loopbac k (rlb ) .......................................................................................................... ........... 31 6.2.2 local loopba ck (llb) ........................................................................................................... ............... 31 6.2.3 analog loopbac k (llb) .......................................................................................................... ............. 31 6.2.4 dual loopba ck (dlb)............................................................................................................ ............... 31 6.3 prbs g eneration and d etection ............................................................................................ 31 6.4 e rror c ounter .......................................................................................................................... 31 6.5 e rror c ounter u pdate ............................................................................................................ 32 6.6 e rror i nsertion ........................................................................................................................ 32 7. analog interface............................................................................................................... .... 33 7.1 r eceiver ............................................................................................................................... ...... 33 7.2 t ransmitter ............................................................................................................................... 33 7.3 j itter a ttenuator ..................................................................................................................... 34 7.4 g.703 s ynchronization s ignal ................................................................................................. 34 8. jtag boundary scan architectur e and test access port .................................. 43 8.1 jtag tap c ontroller s tate m achine .................................................................................... 43 8.2 i nstruction r egister ................................................................................................................ 45 8.3 t est r egisters .......................................................................................................................... 46 9. operating parameters ........................................................................................................ 48 10. ac timing parameters and diagrams.............................................................................. 49 11. pin configurations ............................................................................................................. ... 56 11.1 144-p in bga ............................................................................................................................ 56 11.2 128-p in lqfp........................................................................................................................... 57 12. package information ........................................................................................................... 5 8 12.1 144-b all te-pbga (56-g6020-001) ....................................................................................... 58 12.2 128-p in lqfp (56-g4011-001) ................................................................................................ 59 13. thermal information ............................................................................................................ 60 14. revision history............................................................................................................... ....... 60 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 3 of 60 list of figures figure 1-1. block diagram ...................................................................................................... .................... 5 figure 1-2. receive logic detail ............................................................................................... ................. 6 figure 1-3. transmit logic detail .............................................................................................. ................. 6 figure 4-1. serial port operation for read access (r = 1) mode 1 ......................................................... 16 figure 4-2. serial port operation for read access (r = 1) mode 2 ......................................................... 16 figure 4-3. serial port operation for read access (r = 1) mode 3 ......................................................... 16 figure 4-4. serial port operation for read access (r = 1) mode 4 ......................................................... 17 figure 4-5. serial port operation for write access (r = 0) modes 1 and 2.............................................. 17 figure 4-6. serial port operation for write access (r = 0) modes 3 and 4.............................................. 17 figure 7-1. basic interface .................................................................................................... ................... 36 figure 7-2. protected interface using internal receive termination........................................................ 37 figure 7-3. protected interface using external receive termination....................................................... 38 figure 7-4. dual connector-protected interface using receive termination........................................... 39 figure 7-5. e1 transmit pulse template ......................................................................................... ......... 40 figure 7-6. t1 transmit pulse template ......................................................................................... ......... 41 figure 7-7. jitter tolerance ................................................................................................... ................... 42 figure 7-8. jitter attenuation .................................................................................................................... 42 figure 8-1. jtag block diagram.............................................................................................................. 43 figure 8-2. tap controller state diagram....................................................................................... ......... 44 figure 10-1. intel bus read timing (pbts = 0, bis0 = 0) ....................................................................... 4 9 figure 10-2. intel bus write timing (pbts = 0, bis0 = 0) ....................................................................... 50 figure 10-3. motorola bus timing (pbts = 1, bis0 = 0).......................................................................... 50 figure 10-4. intel bus read timing (pbts = 0, bis0 = 1) ....................................................................... 5 1 figure 10-5. intel bus write timing (pbts = 0, bis0 = 1) ....................................................................... 52 figure 10-6. motorola bus read timing (pbts = 1, bis0 = 1) ................................................................ 52 figure 10-7. motorola bus write timing (pbts = 1, bis0 = 1) ................................................................ 52 figure 10-8. serial bus timing (bis1 = 1, bis0 = 0) ............................................................................ .... 53 figure 10-9. receive-side timing ............................................................................................................ 54 figure 10-10. transmit-side timing ......................................................................................................... 55 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 4 of 60 list of tables table 2-a. bus interface selection ............................................................................................. ................ 7 table 2-b. pin assignments ....................................................................................................................... 7 table 2-c. parallel interface mode pin description............................................................................. ....... 9 table 2-d. serial interface mode pin description ............................................................................... ..... 10 table 2-e. hardware interface mode pin description ............................................................................. .11 table 3-a. ds21448 vs. ds21q348 pin differences ............................................................................... 1 3 table 4-a. loopback control in hardware mode ................................................................................... .. 14 table 4-b. transmit data control in hardware mode.............................................................................. .14 table 4-c. receive sensitivity settings in hardware mode ..................................................................... 14 table 4-d. monitor gain settings in hardware mode .............................................................................. .14 table 4-e. internal rx termination select in hardware mode ................................................................. 14 table 4-f. mclk selection in hardware mode ..................................................................................... ... 15 table 4-g. parallel port mode selection ........................................................................................ .......... 18 table 4-h. register map .......................................................................................................................... 18 table 4-i. receive sensitivity settings ..................................................................................................... 22 table 4-j. backplane clock select.............................................................................................. ............. 22 table 4-k. monitor gain settings ............................................................................................................. 22 table 4-l. internal rx termination select ...................................................................................... .......... 22 table 5-a. received alarm criteria ............................................................................................. ............. 25 table 5-b. receive level indication ............................................................................................ ............. 27 table 6-a. transmit code length ............................................................................................................ 29 table 6-b. receive code length ............................................................................................................. 29 table 6-c. definition of received errors .................................................................................................. 32 table 6-d. function of ecrs bits and rneg pin.................................................................................. .. 32 table 7-a. line build-out select for e1 in register ccr4 (ets = 0) ...................................................... 34 table 7-b. line build-out select for t1 in register ccr4 (ets = 1) ...................................................... 34 table 7-c. line build-out select for e1 in register ccr4 (ets = 0) using alternate transformer configuration...................................................................................................................................... 35 table 7-d. transformer specifications (3.3v operation)......................................................................... .35 table 8-a. instruction codes for ieee 1149.1 architecture ..................................................................... 4 5 table 8-b. id code structure ................................................................................................................... 46 table 8-c. device id codes..................................................................................................................... 46 table 8-d. boundary scan control bits.......................................................................................... .......... 47 table 10-a. ac characteristicsmultiplexed parallel port (bis0 = 0)..................................................... 49 table 10-b. ac characteristicsnonmul tiplexed parallel port (bis0 = 1) .............................................. 51 table 10-c. ac characteristicsserial port (bis1 = 1, bis0 = 0)........................................................... 53 table 10-d. ac characteristicsreceive side .................................................................................... ... 54 table 10-e. ac characteristicstransmit side ................................................................................... ... 55 table 13-a. thermal characteristicsbga ........................................................................................ ..... 60 table 13-b. theta-ja ( ja ) vs. airflowbga ........................................................................................... 60 table 13-c. thermal characteristicslqfp ....................................................................................... .... 60 table 13-d. theta-ja ( ja ) vs. airflowlqfp ......................................................................................... 60 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 5 of 60 1. block diagrams figure 1-1. block diagram v dd v ss power connections 2 2 vco/pll mclk 2.048mhz to 1.544mhz pll jitter attenuator mux vsm tring ttip n filter rring rtip unframed all-ones insertion bis0 control and test port (routed to all blocks) mux (the serial, parallel, and hardware interfaces share device pins) h rst txdis/test 16.384mhz or 8.192mhz or 4.096mhz or 2.048mhz synthesizer bpclk rpos rclk rneg tpos tclk tneg jaclk mux see figure 1-2 see figure 1-3 pbeo mux rcl/lotc typical of all four channels channel 1 channel 2 channel 3 channel 4 jrst jtms jtdi jtdo jtag port jtcl k 8 5 in t cs control and (routed to all blocks) parallel interface sdo scl k serial interface sdi pbts wr (r/ w ) rd ( ds ) ale (as) a0 to a4 d0 to d7/ad0 to ad7 optional terminanation analog loopback line drivers csu filers waveshaping peak detect clock/data recovery remote loopback ( dual mode ) local loopbac k jitter attenuation (can be placed in either transmit or receive path) remote loopbac k dallas semiconductor ds21448 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 6 of 60 figure 1-2. receive logic detail figure 1-3. transmit logic detail rposrneg from remote loopback clock invert rclk ccr2.0 ccr1.6 routed to a ll blocks mux 4 or 8 zero detect 16 zero detect rir1.7 rir1.6 b8zs/hdb3 decoder all-ones detector loop code detector prbs detector sr.6 sr.7 sr.4 rir1.3 ccr2.3 rir1.5 16-bit error counter (ecr) mux ccr6.0 sr.0 ccr6.2/ ccr6.0/ ccr6.1 nrz data bpv/cv/exz pbeo ccr1.4 bpv insert mux b8zs/ hdb3 coder logic error insert mux or gate or ga te ccr3.1 ccr1.6 ccr2.2 ccr3.0 ccr3.4 ccr3.3 tpostneg to remote loopback prbs generator loop code generator clockinvert loss - of - transmit clock detect tclk ccr2.1 rclk jaclk (from mclk) ccr1.0 ccr1.1 ccr1.2 1 0 mux mux or ga te to lotc output pin 0 1 01 a nd gate routed to a ll blocks sr.5 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 7 of 60 2. pin description the ds21448 can be controlled in parallel port mode, serial port mode, or hardware mode. the bus interface select bits 0 and 1 (bis0, bis1) determine the device mode and pin assignments ( table 2-a ). table 2-a. bus interface selection bis1 bis0 bus interface type 0 0 parallel port mode (multiplexed) 0 1 parallel port mode (nonmultiplexed) 1 0 serial port mode 1 1 hardware mode table 2-b. pin assignments pin bga lqfp i/o parallel port mode serial port mode hardware mode j3 18 i cs1 cs1 egl1 d3 57 i cs2 cs2 egl2 d10 84 i cs3 cs3 egl3 k10 114 i cs4 cs4 egl4 j2 91 i rd ( ds ) n/a ets h1 92 i wr ( r /w) n/a nrze k2 95 i ale (as) n/a sclke j1 35 i n/a sclk l2 k3 36 i n/a sdi l1 k1 62 i/o a4 sdo l0 l1 63 i a3 ices dja h11 64 i a2 oces jamux h12 65 i a1 n/a jas g12 66 i a0 n/a hbe j10 75 i/o d7/ad7 n/a ces h10 76 i/o d6/ad6 n/a tpd g11 77 i/o d5/ad5 n/a tx0 j9 78 i/o d4/ad4 n/a tx1 e3 79 i/o d3/ad3 n/a loop0 d4 80 i/o d2/ad2 n/a loop1 f3 81 i/o d1/ad1 n/a mm0 d5 82 i/o d0/ad0 n/a mm1 3 i vsm vsm vsm l5 115C117 vdd1 vdd1 vdd1 e4 19C21 vdd2 vdd2 vdd2 d8 49C51 vdd3 vdd3 vdd3 j8 85C87 vdd4 vdd4 vdd4 m4 118C120 vss1 vss1 vss1 f4 22C24 vss2 vss2 vss2 d9 52C54 vss3 vss3 vss3 h9 88C90 vss4 vss4 vss4 k9 97 i/o int int rt1 k5 110 o pbeo1 pbeo1 pbeo1 g3 111 o pbeo2 pbeo2 pbeo2 e10 121 o pbeo3 pbeo3 pbeo3 k8 123 o pbeo4 pbeo4 pbeo4 l6 126 o rcl1/lotc1 rcl1/lotc1 rcl1 d7 128 o rcl2/lotc2 rcl2/lotc2 rcl2 f9 1 o rcl3/lotc3 rcl3/lotc3 rcl3 j7 2 o rcl4/lotc4 rcl4/lotc4 rcl4 k7 98 i txdis/test txdis/test txdis/test a1 124 i rtip1 rtip1 rtip1 a4 28 i rtip2 rtip2 rtip2 a7 60 i rtip3 rtip3 rtip3 a10 93 i rtip4 rtip4 rtip4 b2 125 i rring1 rring1 rring1 b5 29 i rring2 rring2 rring2 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 8 of 60 pin bga lqfp i/o parallel port mode serial port mode hardware mode b8 61 i rring3 rring3 rring3 b11 94 i rring4 rring4 rring4 l9 106 i hrst hrst hrst j6 109 i mclk mclk mclk h4 122 o bpclk1 bpclk1 bpclk1 d6 47 o bpclk2 bpclk2 bpclk2 f10 56 o bpclk3 bpclk3 bpclk3 l8 112 o bpclk4 bpclk4 bpclk4 l7 107 i bis0 bis0 bis0 m8 68 i bis1 bis1 bis1 a2 6 o ttip1 ttip1 ttip1 a5 38 o ttip2 ttip2 ttip2 a8 71 o ttip3 ttip3 ttip3 a11 102 o ttip4 ttip4 ttip4 j4 7 tvss1 tvss1 tvss1 d1 39 tvss2 tvss2 tvss2 e9 72 tvss3 tvss3 tvss3 l10 103 tvss4 tvss4 tvss4 j5 8 tvdd1 tvdd1 tvdd1 d2 40 tvdd2 tvdd2 tvdd2 g9 73 tvdd3 tvdd3 tvdd3 m9 104 tvdd4 tvdd4 tvdd4 b3 9 o tring1 tring1 tring1 b6 41 o tring2 tring2 tring2 b9 74 o tring3 tring3 tring3 b12 105 o tring4 tring4 tring4 k4 10 o rpos1 rpos1 rpos1 e1 12 o rpos2 rpos2 rpos2 d11 14 o rpos3 rpos3 rpos3 k11 16 o rpos4 rpos4 rpos4 g2 11 o rneg1 rneg1 rneg1 e2 13 o rneg2 rneg2 rneg2 f11 15 o rneg3 rneg3 rneg3 m10 25 o rneg4 rneg4 rneg4 h3 127 o rclk1 rclk1 rclk1 f1 31 o rclk2 rclk2 rclk2 e11 58 o rclk3 rclk3 rclk3 l11 96 o rclk4 rclk4 rclk4 g1 26 i tpos1 tpos1 tpos1 f2 30 i tpos2 tpos2 tpos2 e12 33 i tpos3 tpos3 tpos3 m11 55 i tpos4 tpos4 tpos4 h2 27 i tneg1 tneg1 tneg1 m1 32 i tneg2 tneg2 tneg2 d12 34 i tneg3 tneg3 tneg3 k12 59 i tneg4 tneg4 tneg4 m2 17 i tclk1 tclk1 tclk1 l2 43 i tclk2 tclk2 tclk2 f12 83 i tclk3 tclk3 tclk3 l12 113 i tclk4 tclk4 tclk4 m12 108 i pbts n/a rt0 l3 42 i jtrst jtrst jtrst m3 48 i jtms jtms jtms m5 44 i jtclk jtclk jtclk m6 45 i jtdi jtdi jtdi m7 46 o jtdo jtdo jtdo note 1: the vsm signal is not available with the bga package option. note 2: the lqfp no-connect pin numbers are 4, 5, 37, 67, 69, 70, and 99C101. note 3: the bga no-connect pin numbers are a3, a6, a9, a12, b1, b4, b7, b10, c1Cc12, e5Ce8, f5Cf8, g4Cg8, g10, h5Ch8, j11, j12, k6, and l4. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 9 of 60 table 2-c. parallel interf ace mode pin description pin i/o function rd ( ds ) i read input (data strobe). rd and ds are active-low signals. ds is active low when in nonmultiplexed, motorola mode. see the bus timing diagrams in section 10 . wr (r/ w ) i write input (read/write). wr is an active-low signal. see the bus timing diagrams in section 10 . ale (as) i address latch enable (address strobe). when usi ng multiplexed bus mode (bis0 = 0), this pin serves to demultiplex the bus on a positive-goin g edge. in nonmultiplexed bus mode (bis0 = 1), ale should be wired low. a4Ca0 i address bus. in nonmultiplexed bus operation (bis0 = 1), these pins serve as the address bus. in multiplexed bus operation (bis0 = 0), thes e pins are not used and should be wired low. d7/ad7Cd0/ad0 i/o data bus/address/data bus. in nonmultiplexed bus operation (bis0 = 1), these pins serve as the data bus. in multiplexed bus operation (bis0 = 0) , these pins serve as an 8-bit multiplexed address/data bus. int o interrupt ( int) . the interrupt flags the host controller during conditions and c hange of conditions defined in the status register. it is an active-low, open-drain output. txdis/test i tri-state control, multifunctional. set this pin high, with all cs1 C cs4 inputs inactive, to tri-state ttip1Cttip4 and tring1Ctring4. set this pin high with any of the cs1 C cs4 inputs active to tri-state all outputs and i/o pins (i ncluding the para llel control port). set lo w for normal operation. hrst i hardware reset. bringing hrst low resets the ds21448, setting all control bits to the all-zeros default state. mclk i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data re covery and for jitter attenuation. use of a t1 1.544mhz clock source is optional (note 1). bis0/bis1 i bus interface select bit 0 and 1. used to select bus interface option. see table 2-a for details. pbts i parallel bus type select. when using the paralle l port, set pbts high to select motorola bus timing; set low to select in tel bus timing. this pin controls the function of the rd ( ds ), ale (as), and wr (r/ w ) pins. chip select 1. must be low to read or write to channel 1 of the device. cs1 is an active-low signal. chip select 2. must be low to read or write to channel 2 of the device. cs2 is an active-low signal. chip select 3. must be low to read or write to channel 3 of the device. cs3 is an active-low signal. cs1Ccs4 i chip select 4. must be low to read or write to channel 4 of the device. cs4 is an active-low signal. pbeo1Cpbeo4 o prbs bit-error output. the receiver constantly searches for a 2 15 - 1 (e1) or a qrss (t1) prbs, depending on the ets bit setting (ccr1.7). it remains high if it is out of synchronization with the prbs pattern. it goes low when synchron ized to the prbs pattern. any errors in the received pattern after synchronization cause a pos itive-going pulse (with same period as e1 or t1 clock) synchronous with rclk. prbs bit errors can also be reported to the ecr1 and ecr2 registers by setting ccr6.2 to logic 1. rcl1/lotc1C rcl4/lotc4 o receive carrier loss/loss-of-transmit clock. an output that toggles high during a receive carrier loss (ccr2.7 = 0) or toggles high if t he tclk pin has not been toggled for 5 s 2 s (ccr2.7 = 1). ccr2.7 defaults to logic 0 when in hardware mode. rtip1Crtip4 i rring1Crring4 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect through a 1:1 transformer to the line. see section 7 for details. bpclk1Cbpclk4 o backplane clock. a 16.384mhz, 8.192mhz, 4.096m hz, or 2.048mhz clock output that is referenced to rclk selectable through ccr5.7 and ccr5.6. ttip1Cttip4 o tring1Ctring4 o transmit tip and ring. analog line-driver ou tputs. these pins c onnect through a step-up transformer to the line. see section 7 for details. rpos1Crpos4 o receive positive data. these bits are updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with bipolar data out of the line interface. set nrze (ccr1.6) to 1 for nrz applications. in nrz m ode, data is output on rpos, and a received error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. rneg1Crneg4 o receive negative data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with the bipolar data out of the line interface. set nrze (ccr1.6) to 1 for nrz applications. in nrz mode, data is output on rpos, and a received error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 10 of 60 pin i/o function rclk1Crclk4 o receive clock. buffered recovered clock from t he line. synchronous to mclk in absence of signal at rtip and rring. tpos1Ctpos4 i transmit positive data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. tneg1Ctneg4 i transmit negative data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be transmitted out onto the line. tclk1Ctclk4 i transmit clock. a 2.048mhz or 1.544mhz primary clock. it is used to clock data through the transmit-side formatter. it can be sourced intern ally by mclk or rclk. see common control register 1 and figure 1-3 . jtrst i jtag reset jtms i jtag mode select jtclk i jtag clock jtdi i jtag data in jtdo o jtag data out vsm i voltage supply mode (lqfp only). should be wired low for correct operation. tvdd1Ctvdd4 3.3v, 5% transmitter positive supply vdd1Cvdd4 3.3v, 5% positive supply tvss1Ctvss4 transmitter signal ground vss1Cvss4 signal ground table 2-d. serial interf ace mode pin description pin i/o function int i/o interrupt ( int) . flags host controller during conditions and change of conditions defined in the status register. active-low, open-drain output. txdis/test i tri-state control, multifunctional. set this pin high with all cs1 C cs4 inputs inactive to tri-state ttip1Cttip4 and tring1Ctring4. set this pin high with any of the cs1 C cs4 inputs active to tri-state all outputs and i/o pins (i ncluding the para llel control port). set lo w for normal operation. hrst i hardware reset. bringing hrst low resets the ds21448, setting all control bits to the all-zeros default state. mclk i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data re covery and for jitter attenuation. a t1 1.544mhz clock source is optional (note 1). bis0/bis1 i bus interface select bit 0 and 1. used to select bus interface option. see table 2-a for details. cs1 i chip select 1. must be low to read or write to channel 1 of the device. cs1 is an active-low signal. cs2 i chip select 2. must be low to read or write to channel 2 of the device. cs2 is an active-low signal. cs3 i chip select 3. must be low to read or write to channel 3 of the device. cs3 is an active-low signal. cs4 i chip select 4. must be low to read or write to channel 4 of the device. cs4 is an active-low signal. ices i input clock-edge select. selects whether the serial interface data input (sdi) is sampled on the rising (ices = 0) or falling edge (ices = 1) of sclk. oces i output clock-edge select. selects whether the se rial interface data output (sdo) changes on the rising (oces = 1) or falling edge (oces = 0) of sclk. sclk i serial clock. serial interface clock. sdi i serial data input. serial in terface data input. sdo o serial data output. serial interface data output. pbeo1Cpbeo4 o prbs bit-error output. the receiver constantly searches for a 2 15 - 1 (e1) or a qrss (t1) prbs, depending on the ets bit setting (ccr1.7). it remains high if it is out of synchronization with the prbs pattern. it goes low when synchron ized to the prbs pattern. any errors in the received pattern after synchronization cause a pos itive-going pulse (with same period as e1 or t1 clock) synchronous with rclk. prbs bit errors can also be reported to the ecr1 and ecr2 registers by setting ccr6.2 to logic 1. rcl1/lotc1C rcl4/lotc4 o receive carrier loss/loss-of-transmit clock. an output that toggles high during a receive carrier loss (ccr2.7 = 0) or toggles high if t he tclk pin has not been toggled for 5 s 2 s (ccr2.7 = 1). ccr2.7 defaults to logic 0 when in hardware mode. rtip1Crtip4 rring1Crring4 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect through a 1:1 transformer to the line. see section 7 for details. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 11 of 60 pin i/o function bpclk1Cbpclk4 o backplane clock. a 16.384mhz, 8.192mhz, 4.096m hz, or 2.048mhz clock output that is referenced to rclk selectable through ccr5.7 and ccr5.6. ttip1Cttip4 o tringCtring4 o transmit tip and ring. analog line-driver out puts. these pins connect through a step-up transformer to the line. see section 7 for details. rpos1Crpos4 o receive positive data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with bipolar data out of the line interf ace. set nrze (ccr1.6) to 1 for nrz applications. in nrz mode, data is output on rpos, and a re ceived error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. rneg1Crneg4 o receive negative data. updated on the rising edge (ccr2.0 = 0) or the falling edge (ccr2.0 = 1) of rclk with the bipolar data out of the line interface. set nrze (ccr1.6) to 1 for nrz applications. in nrz mode, data is output on rpos, and a received error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. rclk1Crclk4 o receive clock. buffered recovered clock from t he line. synchronous to mclk in absence of signal at rtip and rring. tpos1Ctpos4 i transmit positive data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be tr ansmitted out onto the line. tneg1Ctneg4 i transmit negative data. sampled on the falling edge (ccr2.1 = 0) or the rising edge (ccr2.1 = 1) of tclk for data to be tr ansmitted out onto the line. tclk1Ctclk4 i transmit clock. a 2.048mhz or 1.544mhz primary cl ock used to clock data through the transmit side formatter. they can be sourced internally by mclk or rclk. see common control register 1 and figure 1-3 . jtrst i jtag reset jtms i jtag mode select jtclk i jtag clock jtdi i jtag data in jtdo o jtag data out vsm i voltage supply mode (lqfp only). vsm should be wired low for correct operation. tvdd1Ctvdd4 3.3v, 5% transmitter positive supply vdd1Cvdd4 3.3v, 5% positive supply tvss1Ctvss4 transmitter signal ground for transmitter outputs vss1Cvss4 signal ground table 2-e. hardware inte rface mode pin description pin i/o function ets i e1/t1 select 0 = e1 1 = t1 nrze i nrz enable 0 = bipolar data at rpos/rneg and tpos/tneg 1 = nrz data at rpos and tpos or tneg; rneg outputs a positive-going pulse when the device receives a bpv, cv, or exz. sclke i receive and transmit synchronization clock enable. sclke combines rsclke (ccr5.3) and tsclke (ccr5.2). 0 = disable 2.048mhz synchronization transmit and receive mode 1 = enable 2.048mhz synchronization transmit and receive mode dja i disable jitter attenuator 0 = jitter attenuator enabled 1 = jitter attenuator disabled jamux i jitter attenuator clock mux. controls the source for jaclk. 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk). 1 = jaclk sourced from internal pll (2.048 mhz at mclk). jas i jitter attenuator path select 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side hbe i receive and transmit hdb3/b8zs enable. hbe combines rhbe (ccr2.3) and thbe (ccr2.2). 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) l0/l1/l2 i line build-out select bits 0,1, and 2. thes e pins set the transmitter build-out; see ( table 7-a (e1) and table 7-b (t1). downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 12 of 60 pin i/o function ces i receive and transmit clock select. selects which rclk edge to update rpos and rneg and which tclk edge to sample tpos and tneg. ces combines tces and rces. 0 = update rpos/rneg on rising edge of rclk; sample tpos/tneg on falling edge of tclk 1 = update rpos/rneg on falling edge of rclk; sample tpos/tneg on rising edge of tclk tpd i transmit power-down 0 = normal transmitter operation 1 = powers down the transmitter and tri-states ttip and tring pins tx0/tx1 i transmit data source select bits 0 and 1. thes e inputs determine the source of the transmit data ( table 4-b ). loop0/loop1 i loopback select bits 0 and 1. t hese inputs determine the active loopback mode ( table 4-a ). mm0/mm1 i monitor mode select bits 0 and 1. these inputs dete rmine if the receive equalizer is in a monitor mode ( table 4-d ). rt1/rt0 i receive liu termination select bits 0 and 1. these inputs determine the receive termination ( table 4-e ). test i tri-state control. set high to tr i-state all outputs and i/o pins (inc luding the parallel control port). set low for normal operation. useful in board-level testing. hrst i hardware reset. bringing hrst low resets the ds21448, setting all control bits to the all-zero default state. mclk i master clock. a 2.048mhz (50ppm) clock source with ttl levels is applied at this pin. this clock is used internally for both clock/data re covery and for jitter attenuation. a t1 1.544mhz clock source is optional (note 1). see table 4-f for details. bis0/bis1 i bus interface select bit 0 and 1. used to select bus interface option ( table 2-a ). egl1Cegl4 i receive equalizer gain-limit select. these bits control the sensitivity of the receive equalizers ( table 4-c ). pbeo1Cpbeo4 o prbs bit-error output. the receiver constantly searches for a 2 15 - 1 prbs (ets = 0) or a qrss prbs (ets = 1). the pattern is chosen autom atically by the value of the ets pin. it remains high if it is out of synchronization with the prbs pattern. it goes low when synchronized to the prbs pattern. any errors in the received pattern after synchronization cause a positive- going pulse (with same period as e1 or t1 clock) synchronous with rclk. rcl1Crcl4 o receive carrier loss. an output that toggles high during a receive carrier loss. rtip1Crtip4 i rring1Crring4 i receive tip and ring. analog inputs for clock recovery circuitry. these pins connect through a 1:1 transformer to the line. see section 7 for details. bpclk1Cbpclk4 o backplane clock. a 16.384mhz clo ck output that is referenced to rclk. ttip1Cttip4 tring1Ctring4 o transmit tip and ring. analog line-driver out puts. these pins connect through a step-up transformer to the line. see section 7 for details. rpos1Crpos4 o receive positive data. updated on the rising edge (ces = 0) or the falling edge (ces = 1) of rclk with bipolar data out of the line interf ace. in nrz mode (nrze = 1), data is output on rpos, and a received error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. rneg1Crneg4 o receive negative data. updated on the rising edge (ces = 0) or the falling edge (ces = 1) of rclk with bipolar data out of the line interf ace. in nrz mode (nrze = 1), data is output on rpos, and a received error (bpv, cv, or exz) causes a positive-going pulse synchronous with rclk at rneg. rclk1Crclk4 o receive clock. buffered recovered clock from t he line. synchronous to mclk in absence of signal at rtip and rring. tpos1Ctpos4 i transmit positive data. sampled on the falling edge (ces = 0) or the rising edge (ces = 1) of tclk for data to be transmitted out onto the line. tneg1Ctneg4 i transmit negative data. sampled on the falling edge (ces = 0) or the rising edge (ces = 1) of tclk for data to be transmitted out onto the line. tclk1Ctclk4 i transmit clock. a 2.048mhz or 1.544mhz primary cl ock used to clock data through the transmit side formatter. it can be sourced internally by mclk or rclk. see common control register 1 and figure 1-3 . jtrst i jtag reset jtms i jtag mode select jtclk i jtag clock jtdi i jtag data in jtdo o jtag data out vsm i voltage supply mode (lqfp only). vsm should be wired low for correct operation. tvdd1Ctvdd4 C 3.3v, 5% transmitter positive supply vdd1Cvdd4 3.3v, 5% positive supply downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 13 of 60 pin i/o function tvss1Ctvss4 transmitter signal ground for transmitter outputs vss1Cvss4 signal ground note 1: g.703 requires an accuracy of 50ppm for t1 and e1. tr62411 and ansi specs require 32ppm accuracy for t1 interfaces. 3. detailed description the ds21448 has a usable receiver sensitivity of 0 to -43db for e1 applications and 0 to -36db for t1 that allows it to operate on 0.63mm (22awg) cables up to 2.5km (e1) and 6000ft (t1) in length. the user has the option to use internal receive termination, software selectable for 75 ? , 100 ? , and 120 ? applications, or external termination. the on-board crystal-less jitter attenuator can be placed in either the transmit or the receive data path, and requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications). the ds21448 has diagnostic capabilities such as loopb acks and prbs pattern generation and detection. 16-bit loop-up and loop-down codes can be gener ated and detected. a single input pin can power down all transmitters to allow the implementation of hitless protection switching (hps) for 1+1 redundancy without the use of relays. the device can be controlled through an 8-bit parallel port (m uxed or nonmuxed) or a serial port, and it can be used in hardware mode. a standard boundary scan interface supports board-level testing. the ds21448 contains four independent lius that share a common interface fo r configuration and status. the user can choose between three different means of accessing the device: a parallel microprocessor interface, a serial interface, and a hardwired mode, which configures the device by setting levels on the devices pins. the ds21448s four chip selects ( cs1 , cs2 , cs3, and cs4 ) determine which liu is accessed when using the parallel or serial interface modes. four sets of identical register maps exist, one for each channel. using the appropriate chip select accesses a channels register map. the analog ami/hdb3 waveform off the e1 line or the ami/b 8zs waveform off the t1 line is transformer-coupled into the rtip and rring pins of the ds21448. the user has the option to use internal termination, software selectable for 75 ? /100 ? /120 ? applications, or external termination. the device recovers clock and data from the analog signal and passes it through the jitter attenuati on mux, outputting the received line clock at rclk and bipolar or nrz data at rpos and rneg. the ds21448 cont ains an active filter that reconstructs the analog- received signal for the nonlinear losses that occur in tr ansmission. the receive circuitry is also configurable for various monitor applications. the device has a usable receiv e sensitivity of 0 to -43db for e1 and 0 to -36db for t1 that allows the device to operate on 0.63mm (22awg) cables up to 2.5km (e1) and 6k feet (t1) in length. data input at tpos and tneg is sent thr ough the jitter attenuation mux to the waveshaping circuitry and line driver. the ds21448 drives the e1 or t1 line from the ttip and trin g pins through a coupling transformer. the line driver can handle both cept 30/isdn-pri lines for e1 and l ong-haul (csu) or short-haul (dsx-1) lines for t1. 3.1 ds21448 and ds21q348 differences the ds21448 bga is a monolithic quad-port liu that is a replacement for the ds21q348. the additional features of jtag, transmit driver disable, and the serial interf ace in the ds21448 have changed the function of several pins, as shown in table 3-a . table 3-a. ds21448 vs. ds21q348 pin differences pin ds21q348 ds21448 g4 vsm n.c. j1 vss sclk k1 a4 a4/sdo k3 vss sdi k7 test txdis/test l3 n.c. jtrst* m3 n.c. jtms* m5 n.c. jtclk m6 n.c. jtdi* m7 n.c. jtdo * ds21448 pin is internally pulled up. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 14 of 60 4. port operation 4.1 hardware mode the ds21448 supports a hardware configuration mode that a llows the user to configure the device by setting levels on the devices pins. this mode allows the ds21448 configuration without the use of a microprocessor, simplifying designs. not all of the device features are supported in the hardware mode. in hardware mode (bis0 = 1, bis1 = 1) several pins have been redefined so they can be used for initializing the ds21448. refer to table 2-b and table 2-e for pin assignment and definition. because of limited pin count, several functions have been combined and affect all four channels in the device and/or treat the receive and transmit paths as one block. restrictions when usi ng the hardware mode include the following: ? bpclk pins only output a 16.384mhz signal. ? the rcl/lotc pins are designated to rcl. ? the rhbe and thbe control bits are combined and controlled by hbe. ? rsclke and tsclke bits are combined and controlled by sclke. ? tces and rces are combined and controlled by ces. ? the transmitter functions are combin ed and controlled by tx1 and tx0. ? loopback functions are controlled by loop1 and loop0. ? jabds defaults to 128-bit buffer depth. ? all other control bits default to logic 0. table 4-a. loopback control in hardware mode loopback symbol loop1 loop0 remote loopback rlb 1 1 local loopback llb 1 0 analog loopback alb 0 1 no loopback 0 0 table 4-b. transmit data control in hardware mode transmit data symbol tx1 tx0 unframed all ones tua1 1 1 alternating ones and zeros taoz 1 0 prbs tprbse 0 1 tpos and tneg 0 0 table 4-c. receive sensitivit y settings in hardware mode egl ets receive sensitivity (db) 0 0 (e1) -12 (short haul) 1 0 (e1) -43 (long haul) 1 1 (t1) -30 (limited long haul) 0 1 (t1) -36 (long haul) table 4-d. monitor gain settings in hardware mode mm1 mm0 internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 table 4-e. internal rx termina tion select in hardware mode rt1 rt0 internal receive termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 120 ? enabled 1 0 internal receive-side 100 ? enabled 1 1 internal receive-side 75 ? enabled downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 15 of 60 table 4-f. mclk select ion in hardware mode mclk (mhz) jamux ets 2.048 0 0 2.048 1 1 1.544 0 1 4.2 serial port operation setting bis1 = 1 and bis0 = 0 enables the serial bus interface on the ds21448 ( table 2-a ). serial port read/write timing is unrelated to the system transmit and receive timi ng, allowing asynchronous reads or writes by the host. see section 10 for the ac timing of the serial port. all serial port accesses are lsb first. see figure 4-1 , figure 4-2 , figure 4-3 , figure 4-4 , figure 4-5 , and figure 4-6 for additional details. a serial bus access requires the use of four signals: serial clock (scl k), one of the four chip selects ( cs ), serial data input (sdi), and serial data output (sdo). the ds21448 uses sclk to sample data that is present on sdi and output data onto sdo. input clock-edge select (ices) a llows the user to choose which sclk edge input data is sampled on. output clock-edge select (oces) allows t he user to choose which sclk edge output data changes on. when ices is low, input data is latched on the rising edge of sclk, and when ices is high, input data is latched on the falling edge of sclk. when oces is low, data is output on the falling edge of sclk, and when oces is high, data is output on the rising edge of sclk. da ta is held until the next falling or rising edge of sclk. all data transfers are initiated by driving the appropriate ports cs input low and ends with cs going inactive. cs must go inactive between data transfers. see the serial bus timing information in section 10 for details. all data transfers are terminated if the ports cs input transitions high. port control l ogic is disabled, and sdo is tri-stated when all cs pins are inactive. reading from or writing to the internal registers requires writing one address/command byte prior to the transferring register data. two types of serial bus transfers exist, standard and burst. the standard serial bus access always consists of two bytes, an address/comm and byte that is always supplied by the user on sdi, and a data byte that can either be written to the ds21448 using sdi (wri te operation) or output by the ds21448 on sdo (read operation). the burst serial bus access consists of a singl e address/command byte followed either by 22 read or 22 write data bytes. the first bit written (lsb) of the address/command byte specif ies whether the access is to be a read (1) or a write (0). the next 5 bits identify the regi ster address. valid register addresses are 00h through 15h. bit 7 is reserved and must be set to 0 for proper operation. bit 8, the last bit (msb) of the address/comm and byte, is the burst mode- enable bit. when the burst bit is enabled (set to 0) and a read operation is performed, the ds21448 automatically outputs the contents of regist ers 00h through 15h sequentially, starting with register address 00h. when the burst bit is enabled and a write operation is performed, data supplied on sdi is sequentially written into the ds21448s register space starting at address 00h. burst oper ation is stopped once address 15h is read or cs goes inactive. for both burst read and burst write transf ers, the address/command bytes regi ster address bits must be set to 0. the user can broadcast register write accesses to mult iple ports simultaneously by enabling the desired channels chip selects at the same time. however, only one port can be read at a time. any attempt to read multiple ports simultaneously results in invalid data being returned on sdo. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 16 of 60 figure 4-1. serial port operatio n for read access (r = 1) mode 1 figure 4-2. serial port operatio n for read access (r = 1) mode 2 figure 4-3. serial port operatio n for read access (r = 1) mode 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 a 1 a 2 a 3 a 4 a 5 0 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s (lsb) (msb) d0 ( lsb ) d7 (msb) read access enabled ices = 1 (sample sdi on the falling edge of sclk) oces = 1 (update sdo on rising edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 a 1 a 2 a 3 a 4 a 5 0 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s (lsb) (msb) d0 ( lsb ) d7 (msb) ices = 1 (sample sdi on the falling edge of sclk) oces = 0 (update sdo on falling edge of sclk) ices = 0 (sample sdi on the rising edge of sclk) oces = 0 (update sdo on falling edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 a 1 a 2 a 3 a 4 a 5 0 b d1 d2 d3 d4 d5 d6 sclk sdi sdo c s (lsb) (msb) d0 (lsb) d7 (msb) downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 17 of 60 figure 4-4. serial port operatio n for read access (r = 1) mode 4 figure 4-5. serial port operation fo r write access (r = 0) modes 1 and 2 figure 4-6. serial port operation fo r write access (r = 0) modes 3 and 4 ices = 0 (sample sdi on the rising edge of sclk) oces = 1 (update sdo on rising edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 a 1 a 2 a 3 a 4 a 5 0 b sclk sdi sdo c s (lsb) (msb) (lsb) (msb) d1 d2 d3 d4 d5 d6 d0 d7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk c s 0 a 1 a 2 a 3 a 4 a 5 0 b (msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled ices = 1 (sample sdi on the falling edge of sclk) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk c s 0 a 1 a 2 a 3 a 4 a 5 0 b (msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled ices = 0 ( sample sdi on the rising edge of sclk ) downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 18 of 60 4.3 parallel port operation the option for either multiplexed bus operation (bis0 = 0) or nonmultiplexed bus operation (bis0 = 1) is available when using the parallel interface. the ds21448 can operate wi th either intel or motorola bus timing configurations. if the pbts pin is wired low, intel timing is selected; if wired high, motorola timing is selected. all motorola bus signals are listed in parentheses (). four sets of id entical register maps exist, one for each channel. see table 4-h for register names and addresses. use the appropriate chip select ( cs1 , cs2 , cs3, or cs4 ) to access a channels register map. see the timing diagrams in section 10 for more details. hardware and serial port modes are not supported when using parallel port operation. 4.3.1 device power-up and reset the ds21448 resets itself upon power-up, setting all wr iteable registers to 00h and clearing the status and information registers. ccr3.7 (tua1) = 0 results in the liu transmitting unframed all ones. after the power supplies have settled, initialize all control registers to the desired settings, then toggle the lirst bit (ccr3.2). the ds21448 can at any time be reset to the default settings by bringing hrst low (level triggered) or by powering down and powering up again. table 4-g. parallel port mode selection pbts bis0 processor bus interface type 0 0 intel parallel port mode (multiplexed) 0 1 intel parallel port mode (nonmultiplexed) 1 0 motorola parallel port mode (multiplexed) 1 1 motorola parallel port mode (nonmultiplexed) 4.3.2 register map table 4-h shows the typical register map for all f our ports. use the appropriate chip select ( cs1 , cs2 , cs3, or cs4 ) to access a channels register map. table 4-h. register map name r/w address function ccr1 r/w 00h common control register 1 ccr2 r/w 01h common control register 2 ccr3 r/w 02h common control register 3 ccr4 r/w 03h common control register 4 ccr5 r/w 04h common control register 5 ccr6 r/w 05h common control register 6 sr r 06h status register imr r/w 07h interrupt mask register rir1 r 08h receive information register 1 rir2 r 09h receive information register 2 ibcc r/w 0ah in-band code control register tcd1 r/w 0bh transmit code definition register 1 tcd2 r/w 0ch transmit code definition register 2 rupcd1 r/w 0dh receive-up code definition register 1 rupcd2 r/w 0eh receive-up code definition register 2 rdncd1 r/w 0fh receive-down code definition register 1 rdncd2 r/w 10h receive-down code definition register 2 ecr1 r 11h error count register 1 ecr2 r 12h error count register 2 test1 r/w 13h test 1 test2 r/w 14h test 2 test2 r/w 15h test 3 (note 1) note 1: register addresses 16hC1fh do not exist. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 19 of 60 4.3.3 control registers ccr1 (00h): common control register 1 (msb) (lsb) ets nrze rcla ecue jamux ttoj ttor lotcmc name position function ets ccr1.7 e1/t1 select 0 = e1 1 = t1 nrze ccr1.6 nrz enable 0 = bipolar data at rpos/rneg and tpos/tneg 1 = nrz data at rpos and tpos or tneg; rneg outputs a positive-going pulse when the device receives a bpv, cv, or exz rcla ccr1.5 receive-carrier-loss alternate criteria 0 = rcl declared upon 255 (e1) or 192 (t1) consecutive zeros 1 = rcl declared upon 2048 (e1) or 1544 (t1) consecutive zeros ecue ccr1.4 error counter update enable. a 0-to-1 transition forces the next receive clock cycle to load the error counter registers with the latest counts and reset the counters. the user must wait a minimum of two clock cycles (976ns for e1 and 1296ns for t1) before reading the error count registers to allow for a proper update. see section 6 for details. jamux ccr1.3 jitter attenuator clock mux. controls the source for jaclk ( figure 1-1 ). 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk) 1 = jaclk sourced from internal pll (2.048mhz at mclk) ttoj ccr1.2 tclk to jaclk. internally connects tclk to jaclk ( figure 1-3 ). 0 = disabled 1 = enabled ttor ccr1.1 tclk to rclk. internally connects tclk to rclk ( figure 1-3 ). 0 = disabled 1 = enabled lotcmc ccr1.0 loss-of-transmit clock mux control. determines whether the transmit logic should switch to jaclk if the tclk input should fail to transition ( figure 1-3 ). 0 = do not switch to jaclk if tclk stops 1 = switch to jaclk if tclk stops downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 20 of 60 ccr2 (01h): common control register 2 (msb) (lsb) rlpin scld clds rhbe thbe tces rces name position function rlpin ccr2.7 rcl/lotc pin function select. forced to logic 0 in hardware mode. 0 = toggles high during a receive-carrier loss condition 1 = toggles high if tclk does not transition for at least 5 s ccr2.6 not assigned. should be set to 0 when written to. scld ccr2.5 short circuit-limit disable (ets = 0). c ontrols the 50ma (rms) current limiter. 0 = enable 50ma current limiter 1 = disable 50ma current limiter clds ccr2.4 custom line-driver select. setting this bit to 1 redefines the operation of the transmit line driver. when this bit is set to 1 and ccr4.5 = ccr4.6 = ccr4.7 = 0, the device generates a square wave at the ttip and tring outputs inst ead of a normal waveform. when this bit is set to 1 and ccr4.5 = ccr4.6 = ccr4.7 0, the device forces ttip and tring outputs to become open-drain drivers instead of their normal push-pull operation. this bit should be set to 0 for normal operation of the device. contact the factory for more details about how to use this bit. rhbe ccr2.3 receive hdb3/b8zs enable 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) thbe ccr2.2 transmit hdb3/b8zs enable 0 = enable hdb3 (e1)/b8zs (t1) 1 = disable hdb3 (e1)/b8zs (t1) tces ccr2.1 transmit clock-edge select. selects which tclk edge to sample tpos and tneg. 0 = sample tpos and tneg on falling edge of tclk 1 = sample tpos and tneg on rising edge of tclk rces ccr2.0 receive clock-edge select. selects which rclk edge to update rpos and rneg. 0 = update rpos and rneg on rising edge of rclk 1 = update rpos and rneg on falling edge of rclk downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 21 of 60 ccr3 (02h): common control register 3 (msb) (lsb) tua1 atua1 taoz tprbse tlce lirst ibpv ibe name position function tua1 ccr3.7 transmit unframed all ones. the polarity of this bi t is set such that the device transmits an all- ones pattern on power-up or device reset. this bit must be set to 1 to allow the device to transmit data. the transmission of this data pattern is always timed off jaclk ( figure 1-1 ). 0 = transmit all ones at ttip and tring 1 = transmit data normally atua1 ccr3.6 automatic transmit unframed all ones. automatica lly transmit an unframed all-ones pattern at ttip and tring during an rcl condition. 0 = disabled 1 = enabled taoz ccr3.5 transmit alternate ones and zeros. transmit a 101010 pattern at ttip and tring. the transmission of this data pattern is always timed off tclk. 0 = disabled 1 = enabled tprbse ccr3.4 transmit prbs enable. transmit a 2 15 - 1 (e1) or a qrss (t1) prbs at ttip and tring. 0 = disabled 1 = enabled tlce ccr3.3 transmit loop-code enable. enables the transmit si de to transmit the loop-up code in the transmit code definition registers (tcd1 and tcd2). see section 6 for details. 0 = disabled 1 = enabled lirst ccr3.2 line interface reset. setting this bi t from 0 to 1 initiates an intern al reset that resets the clock recovery state machine and recenters the jitter attenuator. normally this bit is only toggled on power-up. it must be cleared and set again for a subsequent reset. ibpv ccr3.1 insert bipolar violation (bpv). a 0- to-1 transition on this bit causes a single bipolar violation to be inserted into the transmit data stream. once this bit has been toggled from 0 to 1, the device waits for the next occurrence of three consecutive 1s to insert the bpv. this bit must be cleared and set again for a subsequent error to be inserted ( figure 1-3 ). ibe ccr3.0 insert bit error. a 0-to-1 transition on this bit causes a single logic error to be inserted into the transmit data stream. this bit must be cleared and set again for a subsequent error to be inserted ( figure 1-3 ). ccr4 (03h): common control register 4 (msb) (lsb) l2 l1 l0 egl jas jabds dja tpd name position function l2 ccr4.7 line build-out select bit 2. sets the transmitter build-out ( table 7-a for e1, table 7-b for t1). l1 ccr4.6 line build out select bit 1. sets the transmitter build-out ( table 7-a for e1, table 7-b for t1). l0 ccr4.5 line build out select bit 0. sets the transmitter build-out ( table 7-a for e1, table 7-b for t1). egl ccr4.4 receive equalizer gain limit. this bit c ontrols the sensitivity of the receive equalizer ( table 4-i ). jas ccr4.3 jitter attenuator path select 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side jabds ccr4.2 jitter attenuator buffer depth select 0 = 128 bits 1 = 32 bits (use for delay-sensitive applications) dja ccr4.1 disable jitter attenuator 0 = jitter attenuator enabled 1 = jitter attenuator disabled tpd ccr4.0 transmit power-down 0 = normal transmitter operation 1 = powers down the transmitter and tri-states the ttip and tring pins downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 22 of 60 table 4-i. receive sensitivity settings egl (ccr4.4) ets (ccr1.7) receive sensitivity (db) 0 0 (e1) -12 (short haul) 1 0 (e1) -43 (long haul) 1 1 (t1) -30 (limited long haul) 0 1 (t1) -36 (long haul) ccr5 (04h): common control register 5 (msb) (lsb) bpcs1 bpcs0 mm1 mm0 rsclke tsclke rt1 rt0 name position function bpcs1 ccr5.7 backplane clock frequency select 1. see table 4-j for details. bpcs0 ccr5.6 backplane clock frequency select 0. see table 4-j for details. mm1 ccr5.5 monitor mode gain select 1 ( table 4-k. ) mm0 ccr5.4 monitor mode gain select 0. see ( table 4-k. rsclke ccr5.3 receive synchronization clock enable 0 = disable 2.048mhz synchronization receive mode 1 = enable 2.048mhz synchronization receive mode tsclke ccr5.2 transmit synchronization clock enable 0 = disable 2.048mhz transmit synchronization clock 1 = enable 2.048mhz transmit synchronization clock rt1 ccr5.1 receive termination select 1. see table 4-l for details. rt0 ccr5.0 receive termination select 0. see table 4-l for details. table 4-j. backpla ne clock select bpcs1 (ccr5.7) bpcs0 (ccr5.6) bpclk frequency (mhz) 0 0 16.384 0 1 8.192 1 0 4.096 1 1 2.048 table 4-k. monitor gain settings mm1 (ccr5.5) mm0 (ccr5.4) internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 table 4-l. internal rx termination select rt1 (ccr5.1) rt0 (ccr5.0) internal receive termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 120 ? enabled 1 0 internal receive-side 100 ? enabled 1 1 internal receive-side 75 ? enabled downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 23 of 60 ccr6 (05h): common control register 6 (msb) (lsb) llb rlb arlbe alb rjab ecrs2 ecrs1 ecrs0 name position function llb ccr6.7 local loopback. in local loopback, transmit dat a is looped back to the receive path, passing through the jitter attenuator if it is enabled. data in the transmit path acts as normal. see section 6.2 for details. 0 = loopback disabled 1 = loopback enabled rlb ccr6.6 remote loopback. in remote loopback, data output from the clock/data recovery circuitry is looped back to the transmit path, passing through t he jitter attenuator if it is enabled. data in the receive path acts as normal, while data pr esented at tpos and tneg is ignored. see section 6.2 for details. 0 = loopback disabled 1 = loopback enabled arlbe ccr6.5 automatic remote loopback enable and reset. when this bit is set high, the device automatically goes into remote loopback when it detects loop-up code programmed into the receive loop-up code definition registers (rupcd1 and rupcd2) for a minimum of 5 seconds; it also sets the rir2.1 status bit. once it is in an rl b state, the bit remains in this state until it has detec ted the loop code programmed into the receive loop-down code definition registers (rdncd1 and rdncd2) for a minimum of 5 seconds, at which point it forces the device out of rlb and clears rir2.1. toggling this bit from 1 to 0 resets the automatic rlb circuitry. the action of the auto matic remote loopback ci rcuitry is logically ored with the rlb (ccr6.6) control bit (i.e ., either one can cause a rlb to occur). alb ccr6.4 analog loopback. in analog loopback, signals at ttip and tring are internally connected to rtip and rring. the incoming line signals at rtip and rring are ignored. the signals at ttip and tring are transmitted as normal. see section 6.2 for more details. 0 = loopback disabled 1 = loopback enabled rjab ccr6.3 rclk jitter attenuator bypass. this control bit al lows the receive-recovered clock and data to bypass the jitter attenuation, while still allowing the bpclk output to use the jitter attenuator. see section 7.3 for details. 0 = disabled 1 = enabled ecrs2 ccr6.2 error count register select 2. see section 6.4 for details. ecrs1 ccr6.1 error count register select 1. see section 6.4 for details. ecrs0 ccr6.0 error count register select 0. see section 6.4 for details. 5. status registers the three registers that contain inform ation about the devices real-time stat us are the status register (sr) and receive information registers 1 and 2 (rir1/rir2). when a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. some bits in sr, rir1, and rir2 are latched bits and some are real-time bits (denoted in the following register descripti ons). for latched status bits, when an event or an alarm occurs, the bit is set to 1 and remains set until the user read s that bit. the bit is cleared when it is read, and it is not set until the event has occurred again. two of the latched status bits (rua1 and rcl) remain set after reading if the alarm is still present. the user always precedes a read of any of the three status registers with a write. the byte written to the register informs the ds21448 which bits the user wishes to read and have cleared. the user writes a byte to one of these registers with a 1 in the bit positions to be read and a 0 in the other bit positions. when a 1 is written to a bit location, that location is updated with the latest information. when a 0 is written to a bit position, that bit position is not updated, and the previous value is held. a write to the status and information registers is immediately followed by a read of the same register. the read result should be logically anded with the mask by te that was just written, and this value should be written back into the same regist er to ensure that bit does indeed clear. this second write step is necessary because the alarms and events in the stat us registers occur asynchronously with respect to their access through the parallel port. this wr ite-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bi ts in the register. this operation is key in controlling the ds21448 with higher-order software languages. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 24 of 60 the bits in the sr register have the unique ability to initiate a hardware interrupt through the int output pin. each of the alarms and events in the sr ca n be either masked or unmasked from the interrupt pin through the interrupt mask register (imr). the interrupts caused by the rcl, rua1, and lotc bits in the sr act differently than the interrupts caused by the other st atus bits in the sr. the rcl, rua1, and lotc bits forces the int pin low whenever they change state (i.e., go active or inactive). the int pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present. the other status bits in the sr can force the int pin low when they are set. the int pin is allowed to return high (if no other interrupts are present) when the user reads t he event bit that caused the interrupt to occur. the host can quickly determine which of the four liu channels is generating an interrupt by reading one of the unused addresses in the 16hC1fh range in any liu channel . see the following liu channel interrupt status description for additional information. liu channel interrupt status (msb) (lsb) liu4 liu3 liu2 liu1 name position function n/a 7 not assigned. could be any value when read. n/a 6 not assigned. could be any value when read. n/a 5 not assigned. could be any value when read. n/a 4 not assigned. could be any value when read. liu4 3 liu4 status register. a 1 in this bit position indica tes that the status regist er (sr) in channel 4 is asserting an interrupt. liu3 2 liu3 status register. a 1 in this bit position indica tes that the status regist er (sr) in channel 3 is asserting an interrupt. liu2 1 liu2 status register. a 1 in this bit position indica tes that the status regist er (sr) in channel 2 is asserting an interrupt. liu1 0 liu1 status register. a 1 in this bit position indica tes that the status regist er (sr) in channel 1 is asserting an interrupt. sr (06h): status register (msb) (lsb) lup ldn lotc rua1 rcl tcle tocd prbsd name position function lup (latched) sr.7 loop-up code detected. this bit is set when t he loop-up code defined in registers rupcd1 and rupcd2 is being received. see section 6.1 for details. ldn (latched) sr.6 loop-down code detected. this bit is set when the loop-down code defined in registers rdncd1 and rdncd2 is being received. see section 6.1 for details. lotc (real time) sr.5 loss-of-transmit clock. this bit is set when the tclk pin has not transitioned for 5 s ( 2 s), forcing the lotc pin high. rua1 (latched) sr.4 receive unframed all ones. this bit is set when an unframed all-ones code is received at rring and rtip ( table 5-a ). rcl (latched) sr.3 receive carrier loss. this bit is set when an rcl condition exists at rring and rtip. see ( table 5-a ) for details. tcle (real time) sr.2 transmit current-limit exceeded. this bit is set when the 50ma (rms) current limiter is activated whether or not the current limiter is enabled. tocd (real time) sr.1 transmit open-circuit detect. this bit is set when the device detects that the ttip and tring outputs are open circuited. prbsd (real time) sr.0 prbs detect. this bit is set w hen the receive side detects a 2 15 - 1 (e1) or a qrss (t1) pseudorandom bit sequence (prbs). downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 25 of 60 table 5-a. received alarm criteria alarm e1/t1 set criteria clear criteria rua1 e1 fewer than two 0s in two frames (512 bits) more than two 0s in two frames (512 bits) rua1 t1 over a 3ms window, five or fewer 0s are received. over a 3ms window, six or more 0s are received. rcl (note 1) e1 255 (or 2048) consecutive 0s received (g.775) (note 2) in 255-bit times, at least 32 1s are received. rcl (note 1) t1 192 (or 1544) consecutive 0s are received (note 2) 14 or more 1s out of 112 possible bit positions are received, starting with the first 1 received. note 1: rcl is also known as a loss of signal (los) or red alarm in t1. note 2: see ccr1.5 for details. imr (07h): interrupt mask register (msb) (lsb) lup ldn lotc rua1 rcl tcle tocd prbsd name position function lup imr.7 loop-up code detected 0 = interrupt masked 1 = interrupt enabled ldn imr.6 loop-down code detected 0 = interrupt masked 1 = interrupt enabled lotc imr.5 loss-of-transmit clock 0 = interrupt masked 1 = interrupt enabled rua1 imr.4 receive unframed all ones 0 = interrupt masked 1 = interrupt enabled rcl imr.3 receive carrier loss 0 = interrupt masked 1 = interrupt enabled tcle imr.2 transmit current-limiter exceeded 0 = interrupt masked 1 = interrupt enabled tocd imr.1 transmit open-circuit detect 0 = interrupt masked 1 = interrupt enabled prbsd imr.0 prbs detection 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 26 of 60 rir1 (08h): receive information register 1 (msb) (lsb) zd 16zd hbd rclc rua1c jalt name position function zd (latched) rir1.7 zero detect. this bit is set when a string of at least four (ets = 0) or eight (ets = 1) consecutive 0s (regardless of the length of the string) have been received. this bit is cleared when read. 16zd (latched) rir1.6 16 zero detect. this is set when at least 16 consecutive 0s (regardle ss of the length of the string) have been received. this bit is cleared when read. hbd (latched) rir1.5 hdb3/b8zs word detect. this is set when an hdb3 (ets = 0) or b8zs (ets = 1) codeword is detected independently of the receive hdb3/b8zs mode (ccr4.6) being enabled. this bit is cleared when read. it is useful for automatically setting the line coding. rclc (latched) rir1.4 rcl clear. set when the rcl alarm has met the clear criteria defined in table 5-a . this bit is cleared when read. rua1c (latched) rir1.3 receive unframed all-ones clear. this bit is set when the unframed all-ones signal is no longer detected. this bit is cleared when read ( table 5-a ). jalt (latched) rir1.2 jitter attenuator limit trip. this bit is set when the jitter attenuator fifo reaches within 4 bits of its useful limit. this bit is cleared when read and is useful for debugging jitter attenuation operation. n/a rir1.1 not assigned. could be any value when read. n/a rir1.0 not assigned. could be any value when read. rir2 (09h): receive information register 2 (msb) (lsb) rl3 rl2 rl1 rl0 arlb sec name position function rl3 (real time) rir2.7 receive level bit 3 ( table 5-b ) rl2 (real time) rir2.6 receive level bit 2 ( table 5-b ) rl1 (real time) rir2.5 receive level bit 1 ( table 5-b ) rl0 (real time) rir2.4 receive level bit 0 ( table 5-b ) n/a rir2.3 not assigned. could be any value when read. n/a rir2.2 not assigned. could be any value when read. arlb (real time) rir2.1 automatic remote loopback detected. this bi t is set to 1 when the automatic remote loopback circuitry has detected the presence of a loop-up code for 5 seconds. it remains set until the automatic rlb circuitry has detec ted the loop-down code for 5 seconds. see section 11 for more details. this bit is forced low when the automatic rlb circuitry is disabled (ccr6.5 = 0). sec (latched) rir2.0 one-second timer. this bit is set to 1 on one-second boundaries as timed by the device, based on the rclk. it is cleared when read. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 27 of 60 table 5-b. receive level indication 1 0 0 0 -20.0 to -22.5 1 0 0 1 -22.5 to -25.0 1 0 1 0 -25.0 to -27.5 1 0 1 1 -27.5 to -30.0 1 1 0 0 -30.0 to -32.5 1 1 0 1 -32.5 to -35.0 1 1 1 0 -35.0 to -37.5 1 1 1 1 -37.5 to -40.0 rl3 rl2 rl1 rl0 re ceive level (db) 0 0 0 0 greater than -2.5 0 0 0 1 -2.5 to -5.0 0 0 1 0 -5.0 to -7.5 0 0 1 1 -7.5 to -10.0 0 1 0 0 -10.0 to -12.5 0 1 0 1 -12.5 to -15.0 0 1 1 0 -15.0 to -17.5 0 1 1 1 -17.5 to -20.0 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 28 of 60 6. diagnostics 6.1 in-band loop-code generation and detection the ds21448 can generate and detect a repeating bit pattern from 1 to 8 or 16 bits in length. to transmit a pattern, the user loads the pattern into the transmit code definition (tcd1 and tcd2) registers and selects the proper length of the pattern by setting the tc0 and tc1 bits in the in-band code control (ibcc) register. when generating a 1-, 2-, 4-, 8-, or 16-bit pattern, the transmit code regi sters (tcd1 and tcd2) must be filled with the proper code. generation of a 1-, 3-, 5-, or 7-bit pattern only requires tcd1 to be filled. once this is accomplished, the pattern is transmitted, as long as the tlce control bit (ccr3.3) is enabled. for example, if the user wished to transmit the standard loop-up code for csus, whic h is a repeating pattern of ...10000100 001..., then 80h would be loaded into tcd1, and the length would set using tc1 and tc0 in the ibcc register to 5 bits. the ds21448 can detect two separate repeating patterns to allow for a loop-up code and a loop-down code to be detected. the user programs the codes in the receive-up code definition (rupcd1 and rupcd2) registers and the receive-down code definition (rdncd1 and rdncd2) register s; the length of each pattern is selected through the ibcc register. the ds21448 detects repeating pattern codes with bit-error rates as high as 1 x 10 -2 . the code detector has a nominal integration period of 48ms, so afte r approximately 48ms of receiving either code, the proper status bit (lup at sr.7 and ldn at sr .6) is set to 1. normally codes are sent for a period of 5 seconds. it is recommended that the software poll the ds21448 every 100ms to 1000ms until 5 seconds has elapsed to ensure the code is continuously present. ibcc (0ah): in-band code control register (msb) (lsb) tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 name position function tc1 ibcc.7 transmit code length definition bit 1 ( table 6-a ) tc0 ibcc.6 transmit code length definition bit 0. ( table 6-a) rup2 ibcc.5 receive up code length definition bit 2 ( table 6-b) rup1 ibcc.4 receive-up code length definition bit 1 ( table 6-b ) rup0 ibcc.3 receive-up code length definition bit 0 ( table 6-b ) rdn2 ibcc.2 receive-down code length definition bit 2 ( table 6-b ) rdn1 ibcc.1 receive-down code length definition bit 1 ( table 6-b ) rdn0 ibcc.0 receive-down code length definition bit 0 ( table 6-b ) d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 29 of 60 table 6-a. transmit code length tc1 tc0 length selected (bits) 0 0 5 0 1 6/3 1 0 7 1 1 16/8/4/2/1 table 6-b. receive code length rup2/rdn2 rup1/rdn1 rup0/rdn0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 16/8 tcd1 (0bh): transmit code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 name position function c7 tcd1.7 transmit code definition bit 7. first bit of the repeating pattern. c6 tcd1.6 transmit code definition bit 6 c5 tcd1.5 transmit code definition bit 5 c4 tcd1.4 transmit code definition bit 4 c3 tcd1.3 transmit code definition bit 3 c2 tcd1.2 transmit code definition bit 2. a dont care if a 5-bit length is selected. c1 tcd1.1 transmit code definition bit 1. a dont care if a 5-bit or 6-bit length is selected. c0 tcd1.0 transmit code definition bit 0. a dont care if a 5-, 6-, or 7-bit length is selected. tcd2 (0ch): transmit code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 name position function c15 tcd2.7 transmit code definition bit 15 c14 tcd2.6 transmit code definition bit 14 c13 tcd2.5 transmit code definition bit 13 c12 tcd2.4 transmit code definition bit 12 c11 tcd2.3 transmit code definition bit 11 c10 tcd2.2 transmit code definition bit 10 c9 tcd2.1 transmit code definition bit 9 c8 tcd2.0 transmit code definition bit 8 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 30 of 60 rupcd1 (0dh): receive-up code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 name position function c7 rupcd1.7 receive-up code definition bit 7. first bit of the repeating pattern. c6 rupcd1.6 receive-up code definition bit 6. a dont care if a 1-bit length is selected. c5 rupcd1.5 receive-up code definition bit 5. a don t care if a 1-bit or 2-bit length is selected. c4 rupcd1.4 receive-up code definition bit 4. a don t care if a 1-bit to 3-bit length is selected. c3 rupcd1.3 receive-up code definition bit 3. a don t care if a 1-bit to 4-bit length is selected. c2 rupcd1.2 receive-up code definition bit 2. a don t care if a 1-bit to 5-bit length is selected. c1 rupcd1.1 receive-up code definition bit 1. a don t care if a 1-bit to 6-bit length is selected. c0 rupcd1.0 receive-up code definition bit 0. a don t care if a 1-bit to 7-bit length is selected. rupcd2 (0eh): receive-up code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 name position function c15 rupcd2.7 receive-up code definition bit 15 c14 rupcd2.6 receive-up code definition bit 14 c13 rupcd2.5 receive-up code definition bit 13 c12 rupcd2.4 receive-up code definition bit 12 c11 rupcd2.3 receive-up code definition bit 11 c10 rupcd2.2 receive-up code definition bit 10 c9 rupcd2.1 receive-up code definition bit 9 c8 rupcd2.0 receive-up code definition bit 8 rdncd1 (0fh): receive-down code definition register 1 (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 name position function c7 rdncd1.7 receive-down code definition bit 7. first bit of the repeating pattern. c6 rdncd1.6 receive-down code definition bit 6. a dont care if a 1-bit length is selected. c5 rdncd1.5 receive-down code definition bit 5. a dont care if a 1-bit or 2-bit length is selected. c4 rdncd1.4 receive-down code definition bit 4. a dont care if a 1-bit to 3-bit length is selected. c3 rdncd1.3 receive-down code definition bit 3. a dont care if a 1-bit to 4-bit length is selected. c2 rdncd1.2 receive-down code definition bit 2. a dont care if a 1-bit to 5-bit length is selected. c1 rdncd1.1 receive-down code definition bit 1. a dont care if a 1-bit to 6-bit length is selected. c0 rdncd1.0 receive-down code definition bit 0 . a dont care if a 1-bit to 7-bit length is selected. rdncd2 (10h): receive-down code definition register 2 (msb) (lsb) c15 c14 c13 c12 c11 c10 c9 c8 name position function c15 rdncd2.7 receive-down code definition bit 15 c14 rdncd2.6 receive-down code definition bit 14 c13 rdncd2.5 receive-down code definition bit 13 c12 rdncd2.4 receive-down code definition bit 12 c11 rdncd2.3 receive-down code definition bit 11 c10 rdncd2.2 receive-down code definition bit 10 c9 rdncd2.1 receive-down code definition bit 9 c8 rdncd2.0 receive-down code definition bit 8 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 31 of 60 6.2 loopbacks 6.2.1 remote loopback (rlb) when rlb (ccr6.6) is enabled, the ds21448 is placed into remote loopback. in this loopback, data from the clock/data recovery state machine is looped back to the transmit path, passing through the jitter attenuator if it is enabled. the data at the rpos and rneg pins is valid, whil e data presented at tpos and tneg is ignored. see figure 1-1 for more details. if the automatic rlb enable (ccr6.5) is set to 1, the ds21448 automatically goes into remote loopback when it detects the loop-up code programmed in the receive-up code definition registers (rupcd1 and rupcd2) for a minimum of 5 seconds. when the ds21448 detects the loop-down code programmed in the receive loop-down code definition registers (rdncd1 and rdncd2) for a mini mum of 5 seconds, the ds21448 comes out of remote loopback. setting arlbe to 0 can also disable the arlb. 6.2.2 local loopback (llb) when llb (ccr6.7) is set to 1, the ds21448 is placed into local loopback. in this loopback, data on the transmit side is transmitted as normal. tclk and tpos/tneg pa ss through the jitter attenuator (if enabled) and are output at rclk and rpos/rneg. incoming data from the line at rtip and rring is ignored. if transmit unframed all ones (ccr3.7) is set to 1 while in llb, ttip and tring transmit all ones while tclk and tpos/tneg are looped back to rclk and rpos/rneg. see figure 1-1 for more details. 6.2.3 analog loopback (llb) setting alb (ccr6.4) to 1 puts the ds21448 in analog l oopback. signals at ttip and tring are internally connected to rtip and rring. the incoming signals at rtip and rring are ignored. the signals at ttip and tring are transmitted as normal. see figure 1-1 for more details. 6.2.4 dual loopback (dlb) setting ccr6.7 and ccr6.6 (llb and rlb, respectively) to 1 puts the ds21448 into dual loopback operation. the tclk and tpos/tneg signals are looped back through the jitter attenuator (if enabled) and output at rclk and rpos/rneg. clock and data recovered from rtip and rrin g are looped back to the transmit side and output at ttip and tring. this mode of operation is not av ailable when implementing hardware operation. see figure 1-1 more details. 6.3 prbs generation and detection setting tprbse (ccr3.4) = 1 enables the ds21448 to transmit a 2 15 - 1 (e1) or a qrss (t1) prbs, depending on the ets bit setting in ccr1.7. the ds21448s receive side always searches for these prbs patterns independently of ccr3.4. the prbs bit- error output (pbeo) remains high until the receiver has synchronized to one of the two patterns (64 bits received without an error), at which time pbeo goes low, and the prbsd bit in the sr is set. once synchronized, any bit errors received cause a positive-going pulse at pbeo, synchronous with rclk. this output can be used with external circuitry tr ack bit-error rates during the prbs testing. setting ccr6.2 (ecrs2) = 1 allows the prbs errors to be accumulated in the 16-bit counter in registers ecr1 and ecr2. the prbs synchronizer remains in sync until it experiences six bit errors or more within a 64-bit span. both prbs patterns comply with the itu-t o.151 specifications. 6.4 error counter error count register 1 (ecr1) is the most significant word and ecr2 is the least significant word of a user- selectable 16-bit counter that records incoming er rors, including bpvs, code violat ions (cvs), excessive zero violations (exzs), and/or prbs errors. see table 6-c , table 6-d , and figure 1-2 for details. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 32 of 60 table 6-c. definiti on of received errors error e1 or t1 definition of received errors bpv e1/t1 two consecutive marks with the same polarity . ignores bpvs because of hdb3 and b8zs zero suppression when ccr2.3 = 0. typically used with ami coding (ccr2.3 = 1). itu-t o.161. cv e1 when hdb3 is enabled (ccr2.3 = 0) and the receiver detects two consecutive bpvs with the same polarity. itu-t o.161. exz e1 when four or more cons ecutive zeros are detected. when receiving ami-coded signals (ccr2.3 = 1), detec tion of 16 or more 0s or a bpv. ansi t1.403 1999. exz t1 when receiving b8zs-coded signals (ccr2.3 = 0), det ection of eight or more 0s or a bpv. ansi t1.403 1999. prbs e1/t1 a bit error in a rece ived prbs pattern. see section 6.3 for details. itu-t o.151. table 6-d. function of e crs bits and rneg pin e1 or t1 (ccr1.7) ecrs2 (ccr6.2) ecrs1 (ccr6.1) ecrs0 (ccr6.0) rhbe (ccr2.3) function of ecr counters/rneg (note 1) 0 0 0 0 x cvs 0 0 0 1 x bpvs (hdb3 codewords not counted) 0 0 1 0 x cvs + exzs 0 0 1 1 x bpvs + exzs 1 0 x 0 0 bpvs (b8zs codewords not counted) 1 0 x 1 0 bpvs + 8 exzs 1 0 x 0 1 bpvs 1 0 x 1 1 bpvs + 16 exzs x 1 x x x prbs errors (note 2) note 1: rneg outputs error data only when in nrz mode (ccr1.6 = 1). note 2: prbs errors are always output at pbeo, independent of ecr control bits and nrz mode, and are not present at rneg. 6.5 error counter update a 0-to-1 transition of the ecue (ccr1.4 ) control bit updates the ecr registers with the current va lues and resets the counters. ecue must be set back to 0 and another 0- to-1 transition must occur for subsequent reads/resets of the ecr registers. note that the ds21448 can report errors at rneg when in nrz mode (ccr1.6 = 1) by outputting a pulse for each error occurrence. the counter saturates at 65,535 and does not roll over. ecr1 (11h): upper error count register 1/ ecr2 (12h): lower error count register 2 (msb) (lsb) e15 e14 e13 e12 e11 e10 e9 e8 ecr1 e7 e6 e5 e4 e3 e2 e1 e0 ecr2 name position function e15 ecr1.7 msb of the 16-bit error count. e0 ecr2.0 lsb of the 16-bit error count. 6.6 error insertion when ibpv (ccr3.1) is transitioned from 0 to 1, the devic e waits for the next occurrence of three consecutive 1s to insert a bpv. ibpv must be cleared and se t again for another bpv error insertion. see figure 1-3 for details on the insertion of the bpv into the data stream. when ibe (ccr3.0) is transitioned from 0 to 1, the devic e inserts a logic error. ibe must be cleared and set again for another logic error insertion. see figure 1-2 and figure 1-3 for details about the logic error insertion into the data steam. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 33 of 60 7. analog interface 7.1 receiver the ds21448 contains a digital clock recovery system. th e ds21448 couples to the receive e1 or t1 twisted pair (or coaxial cable in 75 ? e1 applications) through a 1:1 transformer. see table 7-c for transformer details. figure 7-1 , figure 7-2 , figure 7-3 , and table 4-l show the receive termination requirements. the ds21448 has the option of using internal termination resistors. the ds21448 is designed to be fully software selectable for e1 and t1 without the need to change any external resistors for the receive side. the receiv e side allows user configuration for 75 ? , 100 ? , or 120 ? receive termination by setting the rt1 (ccr5.1) and rt0 (ccr5.0) bits. when using the internal termination feature, the r r resistors should be 60 ? each. see figure 7-1 for details. if external termination is required, rt1 and rt0 should be set to 0, and both r r resistors ( figure 7-1 ) should be 37.5 ? , 50 ? , or 60 ? each, depending on the line impedance. the resultant e1 or t1 clock deriv ed from the 2.048/1.544 pll (jaclk in figure 1-1 ) is internally multiplied by 16 through another internal pll and fed to the clock recovery system. the clock recovery sy stem uses the clock from the pll circuit to form a 16-times oversampler used to recover the clock and data. this oversampling technique offers outstanding performance to meet ji tter tolerance specifications, as shown in figure 7-7 . normally, the clock that is output at the rclk pin is the recovered clock from the e1 ami/hdb3 or t1 ami/b8zs waveform presented at the rtip and rring inputs. when no signal is present at rtip and rring, an rcl condition occurs, and the rclk is derived from the jaclk source. see figure 1-1 for more details. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to an approximate 50% duty cycle. if the jitter attenuator is either placed in the transmit path or is disabled, the rclk output can exhibit slightly shorter high cycles of the clock. this is because of the highly oversampled digital clock recovery circuitry. see the receive-side ac timing characteristics in section 10 for more details. the receive-side circuitry also contains a clock synt hesizer that outputs a user-configurable clock (up to 16.384mhz) synthesized from rclk at bpclk (pin 31). see table 4-j for details about output clock frequencies at bpclk. in hardware mode, bpclk defaults to a 16.384mhz output. the ds21448 has a bypass mode for the receive-side clock and data. this allows the bpclk to be derived from rclk after the jitter attenuator, while the clock and data presented at rclk, rpos, and rneg go unaltered. this is intended for applications where the receive-side jitter attenuation is done a fter the liu. setting rjab (ccr6.3) to logic 1 enables the bypass. ensure the jitter attenu ator is in the receiv e path (ccr4.3 = 0). see figure 1-1 for more details. the ds21448 reports the signal strength at rtip and rr ing in 2.5db increments through rl3Crl0 located in the receive information register 2. this feature is helpful when troubleshooting line performance problems ( table 5-b ). e1 and t1 monitor applications require various flat-gain se ttings for the receive-side circuitry. the ds21448 can be programmed to support these applications through the monitor mode control bits mm1 and mm0. when the monitor modes are enabled, the receiver tolerates normal line loss up to -6db ( table 4-k ). 7.2 transmitter the ds21448 uses a set of laser-trimmed delay lines with a precision digital-to-analog converter (dac) to create the waveforms that are transmitted onto the e1 or t1 li ne. the waveforms meet the la test etsi, itu, ansi, and at&t specifications. the user selects which waveform to generate by setting the ets bit (ccr1.7) for e1 or t1 operation, then programming the l2/l1/l0 bits in common cont rol register 4 for the appropriate application. see table 7-a and table 7-b for the proper l2/l1/l0 settings. a 2.048mhz or 1.544mhz ttl clock is required at tclk for transmitting data at tpos and tneg. itu specification g.703 requires 50ppm accuracy for t1 and e1. tr62411 and ansi specs require 32ppm accuracy for t1 interfaces. the clock can be sourced internally by rclk or jaclk. see ccr1.2, ccr1.1, ccr1.0, and figure 1-3 for details. because of the transmitters design, very little jitter (less than 0.005ui p-p broadband from downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 34 of 60 10hz to 100khz) is added to the jitter present on tclk. also, the waveforms created are independent of the duty cycle of tclk. the transmitter couples to the e1 or t1 transmit-twisted pair (or coaxial cable in some e1 applications) through a 1:2 step-up tran sformer. for the device to create t he proper waveforms, the transformer used must meet the sp ecifications listed in table 7-c . the ds21448 has an automatic short-circuit limiter that limits the source current to 50ma (rms) into a 1 ? load. this feature can be disabled by setting the scld bit (ccr 2.5) = 1. when the current limiter is activated, tcle (sr.2) is set even if the short-circuit limiter is disabled. the tpd bit (ccr4.0) powers do wn the transmit-line driver and tri-states the ttip and tring pins . the ds21448 can also detect when the ttip or tring outputs are open circuited. when an open circuit is detected, tocd (sr.1) is set. 7.3 jitter attenuator the ds21448 contains an on-board jitter a ttenuator that can be set to a depth of either 32 or 128 bits through the jabds bit (ccr4.2). the 128-bit mode is used in applicat ions where large excursions of wander are expected. the 32-bit mode is used in delay-sensitive applications. figure 7-8 shows the attenuation characteristics. the jitter attenuator can be placed in either the receive path or the tr ansmit path by appropriately setting or clearing the jas bit (ccr4.3). also, setting the dja bit (c cr4.1) can disable the jitter attenuator (in effect, remove it). for the jitter attenuator to operate properly, a 2.048mh z or 1.544mhz clock must be applie d at mclk. itu specification g.703 requires 50ppm accuracy for t1 and e1. tr62411 and ansi specs require 32ppm accuracy for t1 interfaces. an on-board pll for the jitter attenuator converts the 2.048mhz clock to a 1.544mhz rate for t1 applications. setting jamux (ccr1.3) to logic 0 bypas ses this pll. on-board circuitry adjusts either the recovered clock from the clock/data recovery block or the cl ock applied at the tclk pi n to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclk pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120ui p-p (buffer depth is 128 bits) or 28ui p-p (buffer depth is 32 bits), the ds21448 divides the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jalt bi t in the receive information register 1 (rir1). 7.4 g.703 synchronization signal the ds21448 can receive a 2.048mhz square-wave synchr onization clock, as specified in section 10 of itu g.703. to use the ds21448 in this mode, set the rece ive-synchronization-clock ena ble (ccr5.3) = 1. the ds21448 can also transmit the 2.048mhz square-wave synchronization clock, as specified in section 10 of g.703. to transmit the 2.048mhz clock, set the transmi t-synchronization-clock enable (ccr5.2) = 1. table 7-a. line build-out select fo r e1 in register ccr4 (ets = 0) l2 l1 l0 application n return loss r t ( ? ) 0 0 0 75 ? normal 1:2 n.m. 0 0 0 1 120 ? normal 1:2 n.m. 0 1 0 0 75 ? with high return loss 1:2 21db 6.2 1 0 1 120 ? with high return loss 1:2 21db 11.6 table 7-b. line build-out select for t1 in register ccr4 (ets = 1) l2 l1 l0 application n return loss r t ( ? ) 0 0 0 dsx-1 (0 to 133ft)/0db csu 1:2 n.m. 0 0 0 1 dsx-1 (133 to 266f) 1:2 n.m. 0 0 1 0 dsx-1 (266 to 399ft) 1:2 n.m. 0 0 1 1 dsx-1 (399 to 533ft) 1:2 n.m. 0 1 0 0 dsx-1 (533 to 655ft) 1:2 n.m. 0 1 0 1 -7.5db csu 1:2 n.m. 0 1 1 0 -15db csu 1:2 n.m. 0 1 1 1 -22.5db csu 1:2 n.m. 0 note: see figure 7-1 , figure 7-2 , and figure 7-3 . n.m. = not meaningful. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 35 of 60 table 7-c. line build-out se lect for e1 in register ccr4 (ets = 0) using alternate transformer configuration l2 l1 l0 application n return loss r t ( ? ) 0 0 0 75 ? normal 0.8:1:1ct n.m. 0 0 0 1 120 ? normal 0.8:1:1ct n.m. 0 1 0 0 75 ? with high return loss 0.8:1:1ct 21db 11.6 1 0 1 120 ? with high return loss 0.8:1:1ct 21db 11.6 note: see figure 7-4 . table 7-d. transformer speci fications (3.3v operation) specification recommended value turns ratio 1:1 (receive) and 1:2 (transmit) 2% primary inductance 600 h (min) leakage inductance 1.0 h (max) interwinding capacitance 40pf (max) transmit transformer dc resistance primary (device side) secondary 1.0 ? (max) 1.5 ? (max) receive transformer dc resistance primary (device side) secondary 1.2 ? (max) 1.2 ? (max) downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 36 of 60 figure 7-1. basic interface note 1: all resistor values are 1%. note 2: in e1 applications, the r t resistors are used to increase the transmitter return loss ( table 7-a ). no return loss is requir ed for t1 applications. note 3: the rr resistors should each be set to 60 ? if the internal receive-side termin ation feature is enabled. when this feature is disabled, r r = 37.5 ? for 75 ? or 60 ? for 120 ? e1 systems, or 50 ? for 100 ? t1 lines. note 4: see table 7-a and table 7-b for the appropriate transmit transformer turns ratio (n). v dd v ss ttip tring rtip rring v dd v dd v ss 0.01 f 0.01 f 0.1 f + 10 f 0.1 f r r 0.1 f r t r t 1.0 f (nonpolarized) 2:1 (larger winding toward the network) 1:1 transmit line receive line mclk 2.048mhz (this can also be 1.544mhz for t1 only operation) 68 f r r dallas semiconducto r ds21448 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 37 of 60 figure 7-2. protected interface us ing internal receive termination v dd v ss ttip tring rtip rring dallas semiconducto r ds21448 v dd v dd v ss 0.01 f 0.01 f 0.1 f 68 f + 10 f 0.1 f 60 60 0.1 f s s s s s s s s r t r t 1.0 f (nonpolarized) fuse fuse fuse fuse 2:1 (larger winding toward the network) 1:1 transmit line receive line mclk 2.048mhz (this can also be 1.544mhz for t1 only operation) note 1: all resistor values are 1%. note 2: s is a sidactor. note 3: the fuses are optional to prevent ac power li ne crosses from compromising the transformers. note 4: the r t resistors are used to increase the transmitter return loss ( table 7-a ). no return loss is required for t1 applications. note 5: the 68 f is used to keep the local power plane potential within tolerance duri ng a surge. note 6: refer to a pplication note 324 for sidactor and fuse details. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 38 of 60 figure 7-3. protected interface us ing external receive termination v dd v ss ttip tring rtip rring dallas semiconducto r ds21448 v dd v dd v ss 0.01 f 0.01 f 0.1 f + 10 f 0.1 f s s s s r t r t 1.0 f (nonpolarized) fuse fuse 2:1 (larger winding toward the network) transmit line mclk 2.048mhz (this can also be 1.544mhz for t1 only operation) 0.1 f s s s s fuse fuse 1:1 receive line 470470 68 f r r r r note 1: all resistor values are 1%. note 2: s is a sidactor. note 3: the fuses are optional to prevent ac power li ne crosses from compromising the transformers. note 4: r r = 37.5 ? for 75 ? or 60 ? for 120 ? e1 systems, or 50 ? for 100 ? t1 lines. note 5: the r t resistors are used to increase the transmitter return loss ( table 7-a ). no return loss is required for t1 applications. note 6: the 68 f is used to keep the local power plane potential within tolerance duri ng a surge. note 7: refer to application note 324 for sidactor and fuse details. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 39 of 60 figure 7-4. dual connector-protected interface using receive termination v dd v ss ttip tring rtip rring dallas semiconductor ds21448 v dd v dd v ss 0.01 f 0.01 f 0.1 f + 10 f 0.1 f s r t r t 1.0 f mclk 2.048mhz (this can also be 1.544mhz for t1 only operation) 0.1 f s 68 f 60 60 s s s fuse fuse balanced line (100 ? /120 ? ) unbalanced line (75 ? ) s fuse 0.22 f 0.22 f l1 s s s fuse fuse s fuse 0.22 f 0.22 f l1 0.8:1:1ct 51.1 balanced line (100 ? /120 ? ) unbalanced line (75 ? ) 1:1 0.8:1 1.6:1 2:1 0.8:1:1ct note 1: refer to application note 384 for a complete discussion of this circuit. note 2: all resistor values are 1%. note 3: the fuses are optional to prevent ac power li ne crosses from compromising the transformers. note 4: s is a sidactor. note 5: the r t resistors are used to increase the transmitter return loss ( table 7-c ) . no return loss is required for t1 applications. note 6: the 68 f is used to keep the loca l power plane potential with in tolerance during a surge. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 40 of 60 figure 7-5. e1 transmit pulse template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ? systems, 1.0 on the scale = 2.37v peak in 120 ? systems, 1.0 on the scale = 3.00v peak ) g.703 template downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 41 of 60 figure 7-6. t1 transmit pulse template 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) normalized amplitude t1.102/87, t1.403, cb 119 (oct 79), and i.431 template -0.77-0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500-255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77-0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time a mp. maximum curve ui time a mp. minimum curve downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 42 of 60 figure 7-7. jitter tolerance figure 7-8. jitter attenuation frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k ds21448 tolerance 1 tr 62411 (dec 90) itu-t g.823 frequency (hz) 0 -20 -40 -60 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec 90) prohibited area itu g.7xx prohibited area tbr12 prohibited a rea t1 e1 curve b curve a downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 43 of 60 8. jtag boundary scan architecture a nd test access port the ds21448 ieee 1149.1 des ign supports the standard instruction codes sam ple/preload, bypass, and extest. optional public instructions in cluded are highz, cl amp, and idcode ( table 8-a ). the ds21448 contains the following items, which meet the require ments set by the ieee 1149.1 st andard test access port (tap) and boundary scan architecture: test access port tap controller instruction register bypass register boundary scan register device identification register the tap has the necessary interface pins jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions in section 1 for details. details on boundary scan architecture and the test access port can be found in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. figure 8-1. jtag block diagram 8.1 jtag tap controller state machine this section covers the operation of the tap controller state machine. see figure 8-2 for details on each of the states described below. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk ( table 8-b ). test-logic-reset. upon power-up, the tap controller is in test-logic -reset state. the instru ction register contains the idcode instruction. all system logic of the device operates normally. run-test-idle. the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers remain idle. select-dr-scan. all test registers retain their previous state. wi th jtms low, a rising edge of jtclk moves the controller into the capture- dr state and initiates a scan sequence. jt ms high during a rising edge on jtclk moves the controller to the select-ir-scan state. jtdi jtms jtclk jtrst jtdo test access port controller v dd v dd v dd boundry scan register bypass register instruction register identification register mux select output enable 10k ? 10k ? 10k ? downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 44 of 60 figure 8-2. tap controller state diagram capture-dr. data can be parallel-loaded into the test data regi sters selected by the cu rrent instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. on the rising edge of jtclk, the controller goes to the shift-dr state if jtms is low, or it goes to the exit1-dr state if jtms is high. shift-dr. the test data register selected by the current instruction is connected bet ween jtdi and jtdo, and shifts data one stage toward its serial output on each rising edge of jtclk. if a test regist er selected by the current instruction is not placed in the serial path, it maintains it s previous state. exit1-dr. while in this state, a rising edge on jtclk puts the controller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low puts the controller in the pause- dr state. pause-dr. shifting of the test registers is halted while in this state. all test register s selected by the current instruction retain their previous stat e. the controller remains in this state while jtms is low. a rising edge on jtclk with jtms high puts the co ntroller in the exit2-dr state. exit2-dr. a rising edge on jtclk with jtms high while in this state puts the contro ller in the update-dr state and terminates the scanning process. a rising edge on jtclk with jtms low enters the shift-dr state. update-dr. a falling edge on jtclk while in the update-dr state latches the data from the shift register path of the test registers into the data output latches. this pr events changes at the parallel output due to changes in the shift register. 10 0 1 11 1 11 1 1 11 1 1 00 0 00 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 45 of 60 select-ir-scan. all test registers retain their pr evious state. the instruction r egister remains unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture-ir state and initiates a scan sequence for the instruction register. jtms high duri ng a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir. the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is hi gh on the rising edge of jt clk, the controller enters the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller enters the shift-ir state. shift-ir. in this state, the shift register in the instructi on register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk toward the se rial output. the parallel register and all test registers remain at their previous states. a rising edge on jtclk with jtms high moves the controller to the exit1-ir state. a rising edge on jtclk with jtms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. exit1-ir. a rising edge on jtclk with jtms low puts the controll er in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller enters the u pdate-ir state and terminates the scanning process. pause-ir. shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk puts the controller in the exit2- ir state. the controller remains in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir. a rising edge on jtclk with jtms high puts the contro ller in the update-ir state. the controller loops back to shift-ir if jtms is low during a rising edge of jtclk in this state. update-ir. the instruction code shifted into the instruction sh ift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms low puts th e controller in the run-test-idle state. with jtms high, the controller enters the select-dr-scan state. 8.2 instruction register the instruction register contains a shift register, as well as a latched parallel output, and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low shifts the data one stage toward the serial output at jtdo. a rising edge on jtclk in the exit1-ir st ate or the exit2-ir state with jtms high moves the controller to the update-ir state. the falling edge of that same jtclk latches the data in the instruction shift register to the instruction parallel output. table 8-a shows the instructions s upported by the ds21448 and its respective operational binary codes. table 8-a. instruction cod es for ieee 1149.1 architecture instruction selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 sample/preload. this is a mandatory instruction for the ieee 1149. 1 specification that s upports two functions. the digital i/os of the device can be sampled at the b oundary scan register without interfering with the normal operation of the device by using the c apture-dr state. sample/preload also allows the device to shift data into the boundary scan register through jtdi using the shift-dr state. bypass. when the bypass instruction is latched into the paralle l instruction register, jtdi connects to jtdo through the 1-bit bypass test register. this allows data to pass from jtdi to jtdo without affecting the devices normal operation. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 46 of 60 extest. this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled through the update-ir stat e, the parallel outputs of all digital output pins are driven. the boundary scan register is connected between jtdi and jtdo. the capture- dr samples all digital inputs into the boundary scan register. clamp. all digital outputs of the device are output data from the boundary sc an parallel output while connecting the bypass register between jtdi and jtdo. the ou tputs do not change during the clamp instruction. highz. all digital outputs of the device are placed in a hi gh-impedance state. the bypass register is connected between jtdi and jtdo. idcode. when the idcode instruction is latched into the pa rallel instruction register , the identification test register is selected. the device identif ication code is loaded into the identifi cation register on the rising edge of jtclk following entry into the capture- dr state. shift-dr can be used to shift the identification code out serially through jtdo. during test-logic-reset, the identification code is forced into the instruction registers parallel output. the id code always has a 1 in the lsb position. the next 11 bits identify the manufacturers jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version table 8-b . table 8-c lists the device id code for the sct devices. table 8-b. id code structure msb lsb version (contact factory) device id jedec 1 4 bits 16 bits 00010100001 1 table 8-c. device id codes device 16-bit id ds21448 0018 8.3 test registers ieee 1149.1 requires a minimum of two te st registersthe bypass register and the boundary sc an register. an optional test register, the identificat ion register, has been included with the ds21448 design. it is used with the idcode instruction and the test-logic -reset state of the tap controller. bypass register the bypass register is a single 1-bit shift register used with the bypass, clamp, and highz instructions that provides a short path between jtdi and jtdo. identification register the identification register c ontains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the t ap controller is in the test-logic-reset state. see table 8-b and table 8-c for more information about bit usage. boundary scan register the boundary scan register contains a shift register path an d a latched parallel output for all control cells and digital i/o cells, and is n bits in length. see table 8-d for all cell bit locations and definitions. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 47 of 60 table 8-d. boundary scan control bits pin bit bga lqfp name i/o a1 124 rtip1 i a2 6 ttip1 o a4 28 rtip2 i a5 38 ttip2 o a7 60 rtip3 i a8 71 ttip3 o a10 93 rtip4 i a11 102 ttip4 o b2 125 rring1 i b3 9 tring1 o b5 29 rring2 i b6 41 tring2 o b8 61 rring3 i b9 74 tring3 o b11 94 rring4 i b12 105 tring4 o d1 39 tvss2 d2 40 tvdd2 64 d3 57 cs2 i 48 d4 80 d2/ad2 i/o 46 d5 82 d0/ad0 i/o 67 d6 47 bpclk2 o 22 d7 128 rcl/lotc2 o d8 49C51 vdd3 d9 52C54 vss3 44 d10 84 cs3 i 15 d11 14 rpos3 o 3 d12 34 tneg3 i 17 e1 12 rpos2 o 16 e2 13 rneg2 o 49 e3 79 d3/ad3 i/o e4 19C21 vdd2 e9 72 tvss3 27 e10 121 pbeo3 o 63 e11 58 rclk3 o 4 e12 33 tpos3 i 6 f1 31 rclk2 o 7 f2 30 tpos2 i 47 f3 81 d1/ad1 i/o f4 22C24 vss2 21 f9 1 rcl/lotc3 o 65 f10 56 bpclk3 o 14 f11 15 rneg3 o 45 f12 83 tclk3 i 9 g1 26 tpos1 i 18 g2 11 rneg1 o 31 g3 111 pbeo2 o g9 73 tvdd3 51 g11 77 d5/ad5 i/o pin bit bga lqfp name i/o 54 (note 1) buscntl 56 g12 66 a0 i 42 h1 92 wr (r/ w ) i 8 h2 27 tneg1 i 23 h3 127 rclk1 o 26 h4 122 bpclk1 o h9 88C90 vss4 52 h10 76 d6/ad6 i/o 58 h11 64 a2 i 57 h12 65 a1 i 2 j1 35 sclk i 43 j2 91 rd ( ds ) i 11 j3 18 cs1 i j4 7 tvss1 j5 8 tvdd1 33 j6 109 mclk i 20 j7 2 rcl/lotc4 o j8 85C87 vdd4 50 j9 78 d4/ad4 i/o 53 j10 75 d7/ad7 i/o 60 k1 62 a4 i 41 k2 95 ale (as) i 1 k3 36 sdi i 19 k4 10 rpos1 o 32 k5 110 pbeo1 o 37 k7 98 txdis/test i 25 k8 123 pbeo4 o 39 (note 2) intcntl 38 k9 97 int i/o 28 k10 114 cs4 i 13 k11 16 rpos4 o 62 k12 59 tneg4 i 59 l1 63 a3 i 0 l2 43 tclk2 i l3 42 jtrst i l5 115C117 vdd1 24 l6 126 rcl/lotc1 o 35 l7 107 bis0 i 30 l8 112 bpclk4 o 36 l9 106 hrst i l10 103 tvss4 40 l11 96 rclk4 o 29 l12 113 tclk4 i 5 m1 32 tneg2 i 12 m2 17 tclk1 i m3 48 jtms i m4 118C120 vss1 m5 44 jtclk i downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 48 of 60 pin bit bga lqfp name i/o m6 45 jtdi i m7 46 jtdo o 55 m8 68 bis1 i m9 104 tvdd4 pin bit bga lqfp name i/o 10 m10 25 rneg4 o 61 adrscntl 66 m11 55 tpos4 i 34 m12 108 pbts i note 1: 0 = dn/adn are inputs; 1 = dn/adn are outputs. note 2: 0 = int is an input; 1 = int is an output. 9. operating parameters absolute maximum ratings voltage range on any pin relative to ground -1.0v to +6.0v operating temperature range fo r ds21448tn -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/ jedec j-std-020 specification stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating condi tions for extended periods may affect device reliability. recommended dc op erating conditions (t a = -40c to +85c) parameter symbol conditions min typ max units logic 1 v ih 2.2 5.5 v logic 0 v il -0.3 +0.8 v supply for 3.3v operation v dd (note 1) 3.135 3.3 3.465 v capacitance (t a = +25c) parameter symbol conditions min typ max units input capacitance c in 5 pf output capacitance c out 7 pf dc characteristics (v dd = 3.3v 5%, t a = -40c to +85c.) parameter symbol conditions min typ max units input leakage i il (note 2) -1.0 +1.0 a output leakage i lo (note 3) +1.0 a output current (2.4v) i oh -1.0 ma output current (0.4v) i ol +4.0 ma supply current at 3.3v i dd (notes 4, 5) 320 400 ma power dissipation at 3.3v p dd (notes 4, 5) 1.06 1.32 w note 1: applies to v dd . note 2: 0.0v < v in < v dd . note 3: applied to int when tri-stated. note 4: tclk = mclk = 2.048mhz. note 5: power dissipation with all ports active, ttip and tring driving a 30 ? load, for an all-ones data density. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 49 of 60 10. ac timing parame ters and diagrams table 10-a. ac character isticsmultiplexed parallel port (bis0 = 0) (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 10-1 , figure 10-2 , and figure 10-3 ) parameter symbol conditions min typ max units cycle time t cyc 200 ns pulse width, ds low or rd high pw el 100 ns pulse width, ds high or rd low pw eh 100 ns input rise/fall times t r , t f 20 ns r/ w hold time t rwh 10 ns r/ w setup time before ds high t rws 50 ns cs setup time before ds, wr , or rd active t cs 20 ns cs hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 5 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr, or rd to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr , or rd t ased 10 ns output data delay time from ds or rd t ddr 20 80 ns data setup time t dsw 50 ns figure 10-1. intel bus read timing (pbts = 0, bis0 = 0) ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased c s ad0Cad7 dhr t ddr ale r d w r downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 50 of 60 figure 10-2. intel bus write timing (pbts = 0, bis0 = 0) figure 10-3. motorola bus timing (pbts = 1, bis0 = 0) ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased c s ad0Cad7 r d w r ale t a sd a sh pw t t a sl a hl t cs t a sl t t t dsw dhw t ch t t t ddr dhr rwh t a sed pw eh t rws a hl pw el t cyc a s ds a d0Cad7 (write) a d0Cad7 (read) r/ w c s downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 51 of 60 table 10-b. ac characteristicsnonmul tiplexed parallel port (bis0 = 1) (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 10-4 , figure 10-5 , figure 10-6 , and figure 10-7 ) parameter symbol conditions min typ max units setup time for a0 to a4, valid to cs active t1 0 ns setup time for cs active to either rd , wr , or ds active t2 0 ns delay time from either rd or ds active to data valid t3 75 ns hold time from either rd , wr , or ds inactive to cs inactive t4 0 ns hold time from cs inactive to data bus tri-state t5 5.0 20 ns wait time from either wr or ds active to latch data t6 75 ns data setup time to either wr or ds inactive t7 10 ns data hold time from either wr or ds inactive t8 10 ns address hold from either wr or ds inactive t9 10 ns figure 10-4. intel bus read timing (pbts = 0, bis0 = 1) address valid data valid a0Ca4 d0Cd7 w r c s r d 0ns (min) 0ns (min) 75ns (max) 0ns (min) 5ns (min) / 20ns (max) t1 t2 t3 t4 t5 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 52 of 60 figure 10-5. intel bus write timing (pbts = 0, bis0 = 1) figure 10-6. motorola bus read timing (pbts = 1, bis0 = 1) figure 10-7. motorola bus writ e timing (pbts = 1, bis0 = 1) address valid a0Ca4 d0Cd7 r d c s w r 0ns (min) 0ns (min) 75ns (min) 0ns (min) 10ns (min) 10ns (min) t1 t2 t6 t4 t7 t8 address valid data valid a0Ca4 d0Cd7 r/ w c s d s 0ns (min) 0ns (min) 75ns (max) 0ns (min) 5ns (min) / 20ns (max) t1 t2 t3 t4 t5 address valid a0Ca4 d0Cd7 r/ w c s d s 0ns (min) 0ns (min) 75ns (min) 0ns (min) 10ns (min) 10ns (min) t1 t2 t6 t4 t7 t8 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 53 of 60 table 10-c. ac characteristicsseria l port (bis1 = 1, bis0 = 0) (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 10-8 ) parameter symbol conditions min typ max units setup time cs to sclk t css 50 ns setup time sdi to sclk t sss 50 ns hold time sclk to sdi t ssh 50 ns sclk high/low time t slh 200 ns sclk rise/fall time t srf 50 ns sclk to cs inactive t lsc 50 ns cs inactive time t cm 250 ns sclk to sdo valid t ssv 50 ns sclk to sdo tri-state t sst 100 ns cs inactive to sdo tri-state t csh 100 ns figure 10-8. serial bus ti ming (bis1 = 1, bis0 = 0) sclk (note 1) sclk (note 2) sdi c s high-z sdo t css t sss t ssh t srf t slh t lsc t cm t ssv t sst t csh high-z lsb lsb lsb msb msb msb note 1: oces =1 and ices = 0. note 2: oces = 0 and ices = 1. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 54 of 60 table 10-d. ac charact eristicsreceive side (v dd = 3.3v 5%, t a =-40c to +85c.) ( figure 10-9 ) parameter symbol conditions min typ max units (note 1) 488 rclk period t cp (note 2) 648 ns t ch rclk pulse width t cl (note 3) 200 ns t ch rclk pulse width t cl (note 4) 150 ns delay rclk to rpos, rneg, pbeo, rbpv valid t dd 50.0 ns note 1: e1 mode. note 2: t1 or j1 mode. note 3: jitter attenuator enabled in the receive path. note 4: jitter attenuator disabled or enabled in the transmit path. figure 10-9. receive-side timing t dd rpos, rneg rclk (note 2) cl t t cp ch t rclk (note 1) pbeo t dd bit error bpv/ exz/ cv prbs detector out of sync rneg (note 3) bpv/ exz/ cv note 1: rces = 1 (ccr2.0) or ces = 1. note 2: rces = 0 (ccr2.0) or ces = 0. note 3: rneg is in nrz mode (ccr1.6 = 1). downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 55 of 60 table 10-e. ac characteristicstransmit side (v dd = 3.3v 5%, t a = -40c to +85c.) ( figure 10-10 ) parameter symbol conditions min typ max units (note 5) 488 tclk period t cp (note 6) 648 ns t ch 75 tclk pulse width t cl 75 ns tpos/tneg setup to tclk falling or rising t su 20 ns tpos/tneg hold from tclk falling or rising t hd 20 ns tclk rise and fall times t r , t f 25 ns note 5: e1 mode. note 6: t1 or j1 mode. figure 10-10. transmit-side timing t f t r tpos, tneg t cl t ch cp t hd t su tclk (note 1) t tclk (note 2) note 1: tces = 0 (ccr2.1) or ces = 0. note 2: tces = 1 (ccr2.1) or ces = 1. downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 56 of 60 11. pin configurations 11.1 144-pin te-pbga 1 2 3 4 5 6 7 8 9 10 11 12 a rtip1 ttip1 n.c. rtip2 ttip2 n.c. rtip3 ttip3 n.c. rtip4 ttip4 n.c. b n.c. rring1 tring1 n.c. rring2 tring2 n.c. rring3 tring3 n.c. rring4 tring4 c n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. d tvss2 tvdd2 cs2 d2/ ad2 d0/ ad0 bpclk2 rcl/ lotc2 vdd3 vss3 cs3 rpos3 tneg3 e rpos2 rneg2 d3/ ad3 vdd2 n.c. n.c. n.c. n.c. tvss3 pebo3 rclk3 tpos3 f rclk2 tpos2 d1/ ad1 vss2 n.c. n.c. n.c. n.c. rcl/ lotc3 bpclk3 rneg3 tclk3 g tpos1 rneg1 pebo2 n.c. n.c. n.c. n.c. n.c. tvdd3 n.c. d5/ ad5 a0 h wr (r/ w ) tneg1 rclk1 bpclk1 n.c. n.c. n.c. n.c. vss4 d6/ ad6 a2/ oces a1 j sclk rd ( ds ) cs1 tvss1 tvdd1 mclk rcl/ lotc4 vdd4 d4/ ad4 d7/ ad7 n.c. n.c. k a4/ sdo ale (as) sdi rpos1 pebo1 n.c. txdis/ test pebo4 int cs4 rpos4 tneg4 l a3/ ices tclk2 jtrst n.c. vdd1 rcl/ lotc1 bis0 bpclk4 hrst tvss4 rclk4 tclk4 m tneg2 tclk1 jtms vss1 jtclk jtdi jtdo bis1 tvdd4 rneg4 tpos4 pbts downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 57 of 60 11.2 128-pin lqfp 1 rcl3/lotc3 rcl4/lotc4 vsm n.c. n.c. ttip1 tvss1 tvdd1 tring1 rpos1 rneg1 rpos2 rneg2 rpos3 rneg3 rpos4 tclk1 c s1 / egl1 vdd2 vdd2 10 20 30 vdd2 vss2 vss2 rneg4 vss2 tpos1 tneg1 rtip2 tpos2 rring2 rclk2 tneg2 tpos3 sclk/l2 tneg3 sdi/l1 ttip2 n.c. tvss2 tvdd2 tring2 jtrst tclk2 40 50 60 70 80 90 100 110 120 jtclk jtdi jtdo bpclk2 jtms vdd3 vdd3 vdd3 vss3 vss3 vss3 tpos4 bpclk3 c s2 /egl2 rclk3 tneg4 rtip3 rring3 a 4/sd0/l0 a 3/ices/dja a 2/oces/jamux a 1/jas a 0/hbe n.c. bis1 n.c. n.c. ttip3 tvss3 tvdd3 tring3 d7/ad7/ces d6/ad6/tpd d5/ad5/tx0 d4/ad4/tx1 d3/ad3/loop0 d2/ad2/loop1 d1/ad1/mm0 d0/ad0/mm1 tclk3 c s3 /egl3 vdd4 vdd4 vdd4 vss4 vss4 vss4 r d ( d s )/ets w r (r/ w )/nrze rtip4 rring4 ale (as)/sclke rclk4 i nt / rt1 txdis/test n.c. n.c. n.c. ttip4 tvss4 tvdd4 tring4 h rst bis0 pbts/rt0 mclk pbeo1 pbeo2 bpclk4 tclk4 c s4 /egl4 vdd1 vdd1 vdd1 vss1 vss1 vss1 pbeo3 bpclk1 pbeo4 rtip1 rring1 rcl1/lotc1 rclk1 rcl2/lotc2 dallas semiconductor ds21448 downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 58 of 60 12. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. the package number provided for each package is a link to the latest package outline information.) 12.1 144-ball te-pbga ( 56-g6020-001 ) downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 59 of 60 12.2 128-pin lqfp ( 56-g4011-001 ) downloaded from: http:///
ds21448 3.3v t1/e1/j1 quad line interface 60 of 60 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and s pecification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor. 13. thermal information table 13-a. thermal characteristicsbga parameter min typ max units ambient temperature (note 1) -40 +85 c junction temperature +125 c theta-ja ( ja ) in still air (note 2) +24 c/w table 13-b. theta-ja ( ja ) vs. airflowbga forced air (m/s) theta-ja ( ja ) 0 24c/w 1 21c/w 2.5 19c/w table 13-c. thermal characteristicslqfp parameter min typ max units ambient temperature (note 1) -40 +85 c junction temperature +125 c theta-ja ( ja ) in still air (note 2) +27.8 c/w theta-jc ( jc ) in still air (note 3) +0.1 c/w table 13-d. theta-ja ( ja ) vs. airflowlqfp forced air (m/s) theta-ja ( ja ) 0 27.8c/w 1 23.5c/w 2.5 21.6c/w note 1: the package is mounted on a four-layer jedec-standard test board. note 2: theta-ja ( ja ) is the junction-to-ambient thermal resistance, when the pa ckage is mounted on a four-layer jedec-standard test board. note 3: while theta-jc ( jc ) is commonly used as the thermal parameter that provi des a correlation between the junction temperature (tj) and the average temperature on top center of the lqfp package (tc), the proper term is psi-jt. it is defined by: (tj - tc) / overal l package power. note 4: the method of measurement for the thermal parameters is defined in the eia/jedec-standard document eia-jesd51-2. 14. revision history revision description 042303 new product release. 012104 table 5-b. receive level indication : changed -12.5 to -5.0 to -12.5 to -15.0. adjusted steps after -17.5 db to be in -2.5db decrements. section 9, operating parameters : updated supply current and power dissipation values in the dc characteristics table to reflect latest characterization data. updat ed note 5 to show that values are for all ports active. 113004 in the absolute maximum ratings section, added range for storage temperature and changed soldering temperature from ipc jedec j-std-020a to j-std-020. 011206 added lead-free packages to or dering information table. downloaded from: http:///

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